摘要
为了自动综合设计迭代产生的行为时序,提高综合前后设计时序的一致性,对VHDL同步延时语句的高级综合方法进行研究.将延时转化为适当约束,提出相应调度模型及调度算法,采用启发式方法使解空间搜索算法跳出局部最优,该算法可以在多项式时间复杂度下得到近似最优解.实验结果表明,该算法能有效综合同步延时语句,使综合前后设计时序达到较好一致,提供了一种便于给出延时约束的手段,减少了综合过程的人工干预,提高了设计效率.
The methodology of synthesis of synchronizing statements in VHDL is studied to automatically synthesize behavioral timing generated by design iteration, so as to improve the consistency of timing between the behavioral design and synthesis result. A new scheduling algoritm is presented. The delay time is considered as delay constraints in the algorithm. Scheduling model and corresponding algorithm are also presented. A heuristic method is applied in the algorithm to ensure the algorithm to jump out from local optimization and reach the approximate optimization in polynomial time complexity. It can be concluded from the experimental results that the scheduling algorithm can efficiently synthesize the delay statements and the synthesis result of behavioral design can be more consistent in timing. A convenient means has also been presented to set the timing constraints for synthesis, thus the manual interaction in the synthesis process can be decreased, and the design efficiency can be greatly improved.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2005年第8期692-696,共5页
Transactions of Beijing Institute of Technology
基金
国家自然科学基金资助项目(69973007)
关键词
高级综合
解空间
调度算法
延时约束
high-level synthesis
solution space
scheduling algorithm
delay constraints
