摘要
全数字锁相环设计是相干解调全数字接收机载波同步和位同步的关键技术,而大频偏和低信噪比分别从两个方面增加了环路设计的难度。该文在此背景下,以捕获时间和跟踪性能为指标,从模拟环路分析出发,给出一种适用于大频偏和低信噪比条件的全数字锁相环设计。
The digital phase-locked loops design is a key technology for carrier and bit synchronization in coherent demodulation digital receiver. Large frequency offset and low SNR add more difficulties of the loop design from two different ways. Based on this condition, aim at fast acquisition and tracking, a method of digital loop parameter algorithm is proposed in this paper and some useful conclusions are given.
出处
《电子与信息学报》
EI
CSCD
北大核心
2005年第8期1208-1212,共5页
Journal of Electronics & Information Technology
关键词
数字锁相环
多普勒频偏
低信噪比
同步
Digital Phase-Locked Loop（DPLL）, Doppler frequency offset, Low SNR, Synchronization
