摘要
称为第3代I/O接口技术的PCI Express总线规范的出现,从结构上解决了带宽不足的问题,有着极为广阔的发展前景。基于Verilog HDL硬件描述语言及可综合化设计理念,完成了PCI Express IP核RTL代码的设计。IP核代码使用Verilog HDL语言编写,分模块、分层次地设计了事务层、数据链路层和物理层的逻辑子层,并进行了可综合化设计与代码风格检查。对设计的PCI Express IP核的功能分别从协议层次和应用层次进行了验证。具体实现上,采用Denali公司的PureSuite测试套件对IP核的协议兼容性进行验证,验证范围覆盖了IP核的3个层次以及配置空间,采用QuestaSim仿真工具对IP核的应用层进行验证。仿真结果表明,设计的PCI Express IP核工作正常,性能优良。
The design of RTL code with PCI Express IP core was accomplished on the basis of Verilog HDL and the synthetic design concept.The PCI Express IP core code was compiled with Verilog HDL.The logical sublayers of transaction Layer,data link layer and the physical layer were designed by dividing the modules and layers.The synthetic design and the code style check were performed.The function of PCI Express IP core was verified in the aspects of protocol and application.The compatibility verification of the designed PCI Express IP core was accomplished by the testing assembly PureSuite made by Denali Company,covering the three layers and the Configuration Space of the IP core.The application layer of IP core was verified with the simulation tool QuestaSim.The simulated results show that the PCI Express IP core works well and has satisfactory performance.
出处
《现代电子技术》
2012年第4期123-125,127,共4页
Modern Electronics Technique
