摘要
研究开发了一种准２μｍ高速ＢｉＣＭＯＳ工艺，采用自对准双埋双阱及外延结构．外延层厚度为２．０～２．５μｍ，器件间采用多晶硅缓冲层局部氧化（简称ＰＢＬＯＣＯＳ）隔离，双极器件采用多晶硅发射极（简称ＰＳＥ）晶体管．利用此工艺已试制出ＢｉＣＭＯＳ２５级环振电路，在负载电容ＣＬ＝０．８ｐＦ条件下，平均门延迟时间ｔｐｄ＝０．８４ｎｓ，功耗为０．３５ｍＷ／门，驱动能力为０．６２ｎｓ／ｐＦ．明显优于ＣＭＯＳ门．
A quasi-2 micron high speed BiCMOS proccess has been researched and developed with a self-aligned buried twin well and epitaxy structure.A 2. 0￣2. 5micron epitaxial layer,Poly-Si buffer LOCOS isloation technology, and single poly-Si emitter bipolar transistor are used for high performance of bipolar and CMOS devices.The BiCMOS 25-stage ring oscillators have been fabricated by use of this process.The gate has a 0.84 ns propagation delay time and 0.35mW power dissipation at 0.8pF loading capacitance.Drive ability is 0.62ns/pF,which is greatly superior to that of the equal area CMOS gate.
出处
《微电子学与计算机》
CSCD
北大核心
1995年第3期1-5,共5页
Microelectronics & Computer
关键词
BICMOS
工艺
双极晶体管
High speed,BiCMOS,Poly-Si buffer LOCOS, Poly-Si emitter bipolar transistor
