摘要
通过分析FPGA可配置逻辑块的细致结构,提出了一种基于FPGA的细粒度映射方法,并使用该方法高效实现了大数模乘脉动阵列。在保持高速计算特点的同时,将模乘脉动阵列的资源消耗降低为原来的三分之一。在低成本的20万门级FPGA器件中即可实现1024位模乘器。该实现每秒可进行20次RSA签名。如果换用高性能FPGA,签名速度更可提高至每秒40次。
A fine-grained mapping approach is proposed according to the analysis of the detailed configurable logic block structure of FPGA device, and it is applied to the design of a systolic array for modular multiplication based on FPGA. Without performance losses, the logic resources consumed by the systolic array are reduced to one-third of its o- riginal requirement. By exploiting this approach, it＇s possible to implement a 1024-bit modular multiplier on a 200K gate low-cost FPGA, which can perform 20 1024-bit RSA signature operations per second. Implemented on a high-end FPGA, the modular multiplier can obtain a performance up to 40 signature operations per second.
出处
《微电子学与计算机》
CSCD
北大核心
2005年第7期31-35,41,共6页
Microelectronics & Computer
基金
国家自然科学基金(60273004
60236020)资助
