摘要
采用一种新颖的异步FIFO设计方案,解决FPGA多时钟系统中不同时钟域传输数据的问题。该FIFO实现方案比传统方式简单,工作速度频率高,如设计采用了VerilogHDL硬件语言描述还具有良好的移植性。
In this paper, a new scheme of realization of FIFO which is often used for the transmission of data in multi-asynchronous clock circuits is put forward. The FIFO can work at high speed because it is simple. In addition, the FIFO can be easily replanted for the application of Verilog HDL.
出处
《西华大学学报（自然科学版）》
CAS
2005年第4期77-79,共3页
Journal of Xihua University:Natural Science Edition
关键词
FIFO
异步电路
多时钟系统
亚稳态
FIFO
asynchronous circuit
multi-clock system
metastability
