摘要
本文提出一种模Ｎ计数器的混值编码方案。
A mixed-valued encoding of modulo-N counter is presented, and the al gebraic formulae of designing modulo-N mixed-valued counter by using ternary flipflops in binary construction and binary flip-flops are derived with the help of logic function modification technique.
出处
《计算机学报》
EI
CSCD
北大核心
1994年第A00期109-115,共7页
Chinese Journal of Computers
基金
浙江省自然科学基金
关键词
计数器
模N计数器
混值编码
Multiple-valued logic, mixed-valued encoding, sequential circuits,counter design
