摘要
本文提出了基于FPGA实现傅里叶变换点数可灵活扩展的流水线FFT处理器的结构设计以及各功能模块的算法实现,包括高组合数FFT算法的流水线实现结构、级间混序读/写RAM地址规律、短点数FFT阵列处理结构以及补码实现CORDIC算法的流水线结构等。利用FPGA实现的各功能模块组装了64点FFT处理器。从其计算性能可知,在输入数据速率为20MHz时,利用此结构实现的FFT处理器计算1024点FFT的运算时间约为52μs。
A novel approach for scalable and high-speed Fast Fourier Transform (FFT) processor based on FPGA(Field Programmable Gate-Array) is developed, including the design of the pipeline architecture of FFT and the implementation of its functional elements. The architecture is based on the radix-mixed FFT algorithm for decomposing the long DFT into short length multi-demensional DFTs. The functional elements are the consecutive read-then-write RAM for the implementation of multi-demensional transforms, the short length FFT processor in array architecture and the complement CORDIC(Coordinate Rotation Digital Computer) in pipeline architecture. The conclusion drawn from 64-point FFT processor composed of the elements is that the processor can perform 1024-point FFT every 52μs at 20MHz.
出处
《电讯技术》
2005年第3期147-151,共5页
Telecommunication Engineering
