摘要
用SiCl_4作硅源,在8～13Ω.cm、P型<111>晶向的硅衬底上进行外延。测得锑和硼埋层的漂移率分別约为0.8和1.2。根据测量结果提出克服埋层图形漂移的必要措施,从而使集成电路的成品率得到了显著提高。
Using SiCl_4 as slicon source, we deposited silicon epitaxial on the substrate of p<111>direction 8～13Ω.cm resistivity. The measured shift rate of Sb is about 0.8, while the shift rate of B is about 1.2. We abtained an significant improvement of the dies yield when applying the measurement result described in this paper.
出处
《微电子学与计算机》
CSCD
北大核心
1989年第6期35-36,共2页
Microelectronics & Computer
