摘要
在宽带CDMA(CodeDivisionMultipleAccess码分多址 )系统中 ,卷积码约束长度 (K =9)较大 ,译码时延要求较高 ,如何实现时延短、译码复杂度低、译码存储量少的Viterbi译码器成为新的课题 .本文提出了适合FPGA(FieldProgrammableGateArray现场可编程门阵列 )实现的Viterbi路径度量存储器的存储分裂、最优状态的截短回溯、路径信息循环存储等新颖技术 ,使Viterbi算法既达到了CDMA系统的性能要求 ,又具有译码时延短、译码存储量少的优点 .最后给出了用FPGA实现的Viterbi译码器的实测性能 .
In broadband CDMA system, convolution data with K=9 constrain length should be decoded in real time. A new topic is presented on how to realize short delay, simple structure and low memories of Viterbi decoder. Some new technologies are proposed, such as splitting memories of path metric,short tracing back under best suitable state, storing paths message circularly, which leads to the advantage with low delay and memories. The performance of Viterbi decoder implemented with FPGA is also tested.
出处
《宁波大学学报（理工版）》
CAS
2004年第3期329-331,共3页
Journal of Ningbo University：Natural Science and Engineering Edition
基金
宁波市科委计划项目 (0 0 190 0 2 )
