摘要
VHDL(VHSIC Hardware Description Design Automation)硬件电路描述语言的引入是电子设计 自动化(EDA,Electronic Design Automation)的主要标志。其特点是高层次设计自动化.详细讨论了VHDL几 个方面,并给出了一个实例,同时给出了它的仿真波形时序图.
The introduce of VHDL is the main characteristic of EDA. Its charter is the automation of the design of high digital level. The paper deeply discusses several facets of VHDL;and takes an example and gives its simulation diagram.
出处
《德州学院学报》
2004年第4期56-58,共3页
Journal of Dezhou University
