Using two tripartite Greenberger-Horne-Zeilinger （GHZ） states as the shared channels, we investigate the noise effects on the deterministic joint remote preparation of an arbitrary two-qubit state. By unitary matrix...Using two tripartite Greenberger-Horne-Zeilinger （GHZ） states as the shared channels, we investigate the noise effects on the deterministic joint remote preparation of an arbitrary two-qubit state. By unitary matrix decomposition procedure, we first construct the quantum logic circuit of the deterministic joint remote state preparation protocol. Then, we analytically derive the fidelity and the average fidelity for the deterministic joint remote preparation of an arbitrary two- qubit state and of four types of special two-qubit states under the influence of the Pauli noises. It is found that the fidelity depends on the noise types, the qubit-environment coupling strength, and the state to be remotely prepared. Moreover, even if the two GHZ channels are subject to the same environmental noises, the average fidelities for remotely preparing different two-qubit states display different time evolution behaviors. The remote preparation of the identical two-qubit states also shows that the average fidelities affected by different noisy environments exhibit different evolution actions.展开更多
Due to the waning of Moore’s Law,the conventional monolithic chip architectural design is confronting hurdles such as increasing die size and skyrocketing cost.In this post-Moore era,the integrated chip has emerged a...Due to the waning of Moore’s Law,the conventional monolithic chip architectural design is confronting hurdles such as increasing die size and skyrocketing cost.In this post-Moore era,the integrated chip has emerged as a pivotal technology,gaining substantial interest from both the academia and industry.Compared with monolithic chips,the chiplet-based integrated chips can significantly enhance system scalability,curtail costs,and accelerate design cycles.However,integrated chips introduce vast design spaces encompassing chiplets,inter-chiplet connections,and packaging parameters,thereby amplifying the complexity of the design process.This paper introduces the Optimal Decomposition-Combination Theory,a novel methodology to guide the decomposition and combination processes in integrated chip design.Furthermore,it offers a thorough examination of existing integrated chip design methodologies to showcase the application of this theory.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos.11174081,11034002,11104075,and 11134003)the National Basic Research Program of China (Grant Nos.2011CB921602 and 2012CB821302)the Open Fund from the SKLPS of ECNU
文摘Using two tripartite Greenberger-Horne-Zeilinger （GHZ） states as the shared channels, we investigate the noise effects on the deterministic joint remote preparation of an arbitrary two-qubit state. By unitary matrix decomposition procedure, we first construct the quantum logic circuit of the deterministic joint remote state preparation protocol. Then, we analytically derive the fidelity and the average fidelity for the deterministic joint remote preparation of an arbitrary two- qubit state and of four types of special two-qubit states under the influence of the Pauli noises. It is found that the fidelity depends on the noise types, the qubit-environment coupling strength, and the state to be remotely prepared. Moreover, even if the two GHZ channels are subject to the same environmental noises, the average fidelities for remotely preparing different two-qubit states display different time evolution behaviors. The remote preparation of the identical two-qubit states also shows that the average fidelities affected by different noisy environments exhibit different evolution actions.
基金supported in part by the National Natural Science Foundation of China(NSFC)under Grant 92373206,Grant 62222411,and Grant 62025404in part by the National Key Research and Development Program of China under Grant 2023YFB4404400.
文摘Due to the waning of Moore’s Law,the conventional monolithic chip architectural design is confronting hurdles such as increasing die size and skyrocketing cost.In this post-Moore era,the integrated chip has emerged as a pivotal technology,gaining substantial interest from both the academia and industry.Compared with monolithic chips,the chiplet-based integrated chips can significantly enhance system scalability,curtail costs,and accelerate design cycles.However,integrated chips introduce vast design spaces encompassing chiplets,inter-chiplet connections,and packaging parameters,thereby amplifying the complexity of the design process.This paper introduces the Optimal Decomposition-Combination Theory,a novel methodology to guide the decomposition and combination processes in integrated chip design.Furthermore,it offers a thorough examination of existing integrated chip design methodologies to showcase the application of this theory.
