The increasing pursuit of ultra-high resolution displays has driven the demand for thin film transistors(TFTs)with higher mobility,especially on flexible substrates.In this work,we developed indium tin oxide(ITO)TFTs ...The increasing pursuit of ultra-high resolution displays has driven the demand for thin film transistors(TFTs)with higher mobility,especially on flexible substrates.In this work,we developed indium tin oxide(ITO)TFTs on flexible substrates for the first time and achieved a remarkable average mobility of 39.1 cm^(2)·V^(-1)·s^(-1),via mass-production compatible processes uti-lizing SiO_(2)gate dielectric.Benefiting from the ultra-flat surface and extremely low coefficient of thermal expansion(CTE)of our PI substrate,the ITO TFTs exhibit excellent large-scale uniformity.Additionally,the TFTs generate minor variations of-5.5%and+0.45 V in mobility and threshold voltage under a bending radius of 7 mm,respectively.They stay fully functional even after a dynamic bending test up to 13000 cycles,observing no obvious degradation in mobility and threshold voltage.The reliable mechanical flexibility and robust bending durability demonstrate their great potential for ultra-high resolution flexible displays in the future.展开更多
In this work,we demonstrated the InSnO(ITO)TFTs passivated with SiO_(2)via the PECVD process compatible with large-area production for the first time.The passivated ITO TFTs with various channel thicknesses(t_(ch)=4,5...In this work,we demonstrated the InSnO(ITO)TFTs passivated with SiO_(2)via the PECVD process compatible with large-area production for the first time.The passivated ITO TFTs with various channel thicknesses(t_(ch)=4,5,6 nm)exhibit excellent electrical performance and superior uniformity.The reliability properties of ITO TFTs were evaluated in detail under positive bias stress(PBS)conditions before and after passivation.Compared to the devices without passivation,the passivated devices have only 50%threshold voltage degradation(ΔV_(th))and 50%newly generated traps due to excellent isolation of the ambient atmosphere.The negligible performance degradation of ITO TFTs with passivation during negative bias stress(NBS)and negative bias temperature stress(NBTS)verifies the outstanding immunity to the water vapor of the SiO_(2)passivation layer.Overall,the ITO TFT with the t_(ch)of 6 nm and with SiO_(2)passivation exhibits the best performance in terms of electrical properties,uniformity,and reliability,which is promising in large-area production.展开更多
Due to the fact that the register files seriously affect the performance and area of coarse-grained reconfigurable cryptographic processors, an efficient structure of the distributed cross-domain register file is prop...Due to the fact that the register files seriously affect the performance and area of coarse-grained reconfigurable cryptographic processors, an efficient structure of the distributed cross-domain register file is proposed to realize a cryptographic processor with a high performance and a lowarea cost. In order to meet the demands of high performance and high flexibility at a lowarea cost, a union structure with the multi-ports access structure, i, e., a distributed crossdomain register file, is designed by analyzing the algorithm features of different ciphers. Considering different algorithm requirements of the global register files and local register files,the circuit design is realized by adopting different design parameters under TSMC( Taiwan Semiconductor Manufacturing Company) 40 nm CMOS( complementary metal oxide semiconductor) technology and compared with other similar works. The experimental results showthat the proposed distributed cross-domain register structure can effectively improve the performance of the unit area, of which the total performance of block per cycle is improved by17. 79% and performance of block per cycle per area is improved by 117%.展开更多
Due to the shared nature of the wireless medium, the performance of wireless sensor network is often limited by both internal interference and external interference. The internal interference is that simultaneous traf...Due to the shared nature of the wireless medium, the performance of wireless sensor network is often limited by both internal interference and external interference. The internal interference is that simultaneous traffic activity by neighboring nodes in the same network, while the external interference is from wireless transmissions by other types of devices, such as Wi-Fi and Bluetooth nodes. In this paper, we present two channel hopping algorithms for multichannel, single-radio wireless sensor networks. The first algorithm achieves collision-free transmission environment while do not introduce extra control overhead. The second algorithm, in addition to reducing internal interference effects, reduces the external interference effects from Wi-Fi devices. Simulation results show that both of them significantly improve performance in wireless sensor network.展开更多
This paper proposes an improved method for the prediction of radial vibration in switched reluctance motor(SRM)considering magnetic saturation.In this paper,the basic modeling principle is briefly introduced,it is bas...This paper proposes an improved method for the prediction of radial vibration in switched reluctance motor(SRM)considering magnetic saturation.In this paper,the basic modeling principle is briefly introduced,it is based on the derivation that the peak acceleration is dependent on the product of phase current and current gradient idi/dt.However,the derivation may cause errors due to saturation effect.Thus in this paper,the discrete sample data are firstly acquired based on DC pulse measurement method,by which electromagnetic,torque and peak acceleration characteristics can all be acquired.Then the entire peak acceleration characteristics are obtained by improved Least Square Support Vector Machine(LSSVM).Based on the obtained static peak acceleration characteristics,the time-varied radial vibration model is established based on superposition of natural oscillations of dominant vibration modes.Finally,a simulation model is built up using MATLAB/Simulink.The good agreement between simulation and experiment shows that the proposed method for modeling is feasible and accurate,even under saturation.In addition,since LSSVM does not need any prior knowledge,it is much easier for modeling compared with other existing literatures.展开更多
The radiation influences on electrical parameters of4H-SiC vertical double-implanted metal-oxide-semiconductor field effect transistor( VDMOS) are studied. By simulations on SRIM software and SILVACO software, the ele...The radiation influences on electrical parameters of4H-SiC vertical double-implanted metal-oxide-semiconductor field effect transistor( VDMOS) are studied. By simulations on SRIM software and SILVACO software, the electrical parameters shifts of the device with defects in different regions are observed. The results indicate that the defects in different regions induced by radiations lead to different degradations of the electrical parameters. Non-ionization bulk defects in the JFET region make the drain-source on-state resistance Rdson increase,and those near the impact ionization center make the breakdown voltage Vbreakdownincrease. Moreover,the radiationinduced SiC/SiO2 interface defects,known as negative interface charges or positive interface charges,influence the electrical parameters significantly as well. The positive interface charges along the SiC/SiO2 interface above the channel region lead to a decrease in threshold voltage Vth,Rdsonand Vbreakdown,while positive interface charges along the Si C/Metal interface above the main junction of the terminal only leads to the decrease in Vbreakdown. The negative interface charges along the SiC/SiO2 interface above the channel region can make Vth,Rdsonand Vbreakdownincrease.展开更多
The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide ...The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.展开更多
Si p^+n junction diodes operating in the mode of avalanche breakdown are capable of emitting light in the visible range of 400-900 nm. In this study, to realize the switching speed in the GHz range, we present a trans...Si p^+n junction diodes operating in the mode of avalanche breakdown are capable of emitting light in the visible range of 400-900 nm. In this study, to realize the switching speed in the GHz range, we present a transient model to shorten the carrier lifetime in the high electric field region by accumulating carriers in both p and n type regions. We also verify the optoelectronic characteristics by disclosing the related physical mechanisms behind the light emission phenomena. The emission of visible light by a monolithically integrated Si diode under the reverse bias is also discussed. The light is emitted as spatial sources by the defects located at the p-n junction of the reverse-biased diode. The influence of the defects on the electrical behavior is manifested as a current-dependent electroluminescence.展开更多
This paper is devoted to temperature analysis on power RF LDMOS with different feature parameters of die thickness, pitch S length and finger width. The significance of these three parameters is determined from temper...This paper is devoted to temperature analysis on power RF LDMOS with different feature parameters of die thickness, pitch S length and finger width. The significance of these three parameters is determined from temperature comparison obtained by 3D Silvaco-Atlas device simulator. The first three simulations focus on temperature variation with the three factors at different output power density respectively. The results indicate that both the thinner die thickness and the broaden pitch S length have distinct advantages over the shorter finger width. The device, at the same time, exhibits higher temperature at a larger output power density. Simulations are further carried out on structure with combination of different pitch s length and die thickness at a large 1W/mm output power density and the temperature reduction reaches as high as 55%.展开更多
The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. ...The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface （VPI） and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.展开更多
A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-couple...A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt.In addition,a differential noise cancellation circuit is proposed to enhance the noise immunity further.Meanwhile,the negative V_S capacity is improved by unifying the detected reference voltage and the logic block＇s threshold voltage.A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.展开更多
A high-order curvature-compensated CMOS bandgap reference（BGR） topology with a low temperature coefficient（TC） over a wide temperature range and a high power supply reject ratio（PSRR） is presented.High-order cor...A high-order curvature-compensated CMOS bandgap reference（BGR） topology with a low temperature coefficient（TC） over a wide temperature range and a high power supply reject ratio（PSRR） is presented.High-order correction is realized by incorporating a nonlinear current INL, which is generated by ？V_（GS） across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of0.19 ppm/°C over the temperature range of 165 °C（-40 to 125 °C）, PSRR of-123 d B @ DC and-56 d B @ 100 k Hz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.展开更多
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work pr...The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.展开更多
A fully integrated soft-start circuit for DC-DC buck converters is presented. The proposed high speed soft-start circuit is made of two sections： an overshoot suppression circuit and an inrush current suppression cir...A fully integrated soft-start circuit for DC-DC buck converters is presented. The proposed high speed soft-start circuit is made of two sections： an overshoot suppression circuit and an inrush current suppression circuit. The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DC-DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13 um CMOS process. Experimental results show that the proposed high speed soft-start circuit has achieved less than 50 us start-up time. The inductor current and the output voltage increase smoothly over the whole load range.展开更多
We present a novel gated operation active quenching circuit （AQC）. In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I-V characteristic measurement resuits...We present a novel gated operation active quenching circuit （AQC）. In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I-V characteristic measurement resuits of the detector. The circuit integrated with a ROIC （readout integrated circuit） is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications.展开更多
A novel digital control algorithm for digital control power factor correction is presented, which is called the prediction algorithm and has a feature of a higher PF （power factor） with lower total harmonic distorti...A novel digital control algorithm for digital control power factor correction is presented, which is called the prediction algorithm and has a feature of a higher PF （power factor） with lower total harmonic distortion, and a faster dynamic response with the change of the input voltage or load current. For a certain system, based on the current system state parameters, the prediction algorithm can estimate the track of the output voltage and the inductor current at the next switching cycle and get a set of optimized control sequences to perfectly track the trajectory of input voltage. The proposed prediction algorithm is verified at different conditions, and computer simulation and experimental results under multi-situations confirm the effectiveness of the prediction algorithm. Under the circumstances that the input voltage is in the range of 90-265 V and the load current in the range of 20%-100%, the PF value is larger than 0.998. The 0.02 s without overshoot. The experimental results startup and the recovery times respectively are about 0.1 s and also verify the validity of the proposed method.展开更多
A sub-circuit SPICE model of a MOSFET for low temperature operation is presented.Two resistors are introduced for the freeze-out effect,and the explicit behavioral models are developed for them.The model can be used i...A sub-circuit SPICE model of a MOSFET for low temperature operation is presented.Two resistors are introduced for the freeze-out effect,and the explicit behavioral models are developed for them.The model can be used in a wide temperature range covering both cryogenic temperature and regular temperatures.展开更多
A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabr...A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabricated in an SMIC 0.13 μm CMOS process with only MOS transistors and resistors. The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from -20 to 120 ℃C. The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8 μA at room temperature. The occupied area is only 0.019 mm^2.展开更多
The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons： one is over-etchi...The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons： one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon comer of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon comers at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry＇s 0.5-μm HV SOI technology.展开更多
The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC-DC converters. The control method provides pre-estimations of the duty ratio in the next sever...The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC-DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC-DC with the proposed prediction is about 8/μs when the load current changes from 0.6 to 0.1A.展开更多
基金supported in part by the National Natural Science Foundation of China(62274033)Natural Science Foundation of Jiangsu Province(BK20221453)Fundamental Research Funds for the Central Universities.
文摘The increasing pursuit of ultra-high resolution displays has driven the demand for thin film transistors(TFTs)with higher mobility,especially on flexible substrates.In this work,we developed indium tin oxide(ITO)TFTs on flexible substrates for the first time and achieved a remarkable average mobility of 39.1 cm^(2)·V^(-1)·s^(-1),via mass-production compatible processes uti-lizing SiO_(2)gate dielectric.Benefiting from the ultra-flat surface and extremely low coefficient of thermal expansion(CTE)of our PI substrate,the ITO TFTs exhibit excellent large-scale uniformity.Additionally,the TFTs generate minor variations of-5.5%and+0.45 V in mobility and threshold voltage under a bending radius of 7 mm,respectively.They stay fully functional even after a dynamic bending test up to 13000 cycles,observing no obvious degradation in mobility and threshold voltage.The reliable mechanical flexibility and robust bending durability demonstrate their great potential for ultra-high resolution flexible displays in the future.
基金supported in part by the National Natural Science Foundation of China(62404110,62274033)Natural Science Foundation of Jiangsu Province(BK20221453)+1 种基金Fundamental Research Funds for the Central UniversitiesNatural Science Research Start-up Foundation of Recruiting Talents of Nanjing University of Posts and Telecommunications(NY223159)。
文摘In this work,we demonstrated the InSnO(ITO)TFTs passivated with SiO_(2)via the PECVD process compatible with large-area production for the first time.The passivated ITO TFTs with various channel thicknesses(t_(ch)=4,5,6 nm)exhibit excellent electrical performance and superior uniformity.The reliability properties of ITO TFTs were evaluated in detail under positive bias stress(PBS)conditions before and after passivation.Compared to the devices without passivation,the passivated devices have only 50%threshold voltage degradation(ΔV_(th))and 50%newly generated traps due to excellent isolation of the ambient atmosphere.The negligible performance degradation of ITO TFTs with passivation during negative bias stress(NBS)and negative bias temperature stress(NBTS)verifies the outstanding immunity to the water vapor of the SiO_(2)passivation layer.Overall,the ITO TFT with the t_(ch)of 6 nm and with SiO_(2)passivation exhibits the best performance in terms of electrical properties,uniformity,and reliability,which is promising in large-area production.
基金The National Natural Science Foundation of China(No.61176024)
文摘Due to the fact that the register files seriously affect the performance and area of coarse-grained reconfigurable cryptographic processors, an efficient structure of the distributed cross-domain register file is proposed to realize a cryptographic processor with a high performance and a lowarea cost. In order to meet the demands of high performance and high flexibility at a lowarea cost, a union structure with the multi-ports access structure, i, e., a distributed crossdomain register file, is designed by analyzing the algorithm features of different ciphers. Considering different algorithm requirements of the global register files and local register files,the circuit design is realized by adopting different design parameters under TSMC( Taiwan Semiconductor Manufacturing Company) 40 nm CMOS( complementary metal oxide semiconductor) technology and compared with other similar works. The experimental results showthat the proposed distributed cross-domain register structure can effectively improve the performance of the unit area, of which the total performance of block per cycle is improved by17. 79% and performance of block per cycle per area is improved by 117%.
基金supported by the Natural Science Foundation of China(No.61574035)National Natural Science Foundation of China(No.61550110244)
文摘Due to the shared nature of the wireless medium, the performance of wireless sensor network is often limited by both internal interference and external interference. The internal interference is that simultaneous traffic activity by neighboring nodes in the same network, while the external interference is from wireless transmissions by other types of devices, such as Wi-Fi and Bluetooth nodes. In this paper, we present two channel hopping algorithms for multichannel, single-radio wireless sensor networks. The first algorithm achieves collision-free transmission environment while do not introduce extra control overhead. The second algorithm, in addition to reducing internal interference effects, reduces the external interference effects from Wi-Fi devices. Simulation results show that both of them significantly improve performance in wireless sensor network.
基金This work was supported by the National Natural Science Foundation of China under Grant 51277026 and 61674033Natural Science Foundation of Jiangsu Province under Grant BK20161148the Scientific Research Foundation of Graduate School of Southeast University under Grant YBJJ1822.(Corresponding author:Weifeng Sun.)。
文摘This paper proposes an improved method for the prediction of radial vibration in switched reluctance motor(SRM)considering magnetic saturation.In this paper,the basic modeling principle is briefly introduced,it is based on the derivation that the peak acceleration is dependent on the product of phase current and current gradient idi/dt.However,the derivation may cause errors due to saturation effect.Thus in this paper,the discrete sample data are firstly acquired based on DC pulse measurement method,by which electromagnetic,torque and peak acceleration characteristics can all be acquired.Then the entire peak acceleration characteristics are obtained by improved Least Square Support Vector Machine(LSSVM).Based on the obtained static peak acceleration characteristics,the time-varied radial vibration model is established based on superposition of natural oscillations of dominant vibration modes.Finally,a simulation model is built up using MATLAB/Simulink.The good agreement between simulation and experiment shows that the proposed method for modeling is feasible and accurate,even under saturation.In addition,since LSSVM does not need any prior knowledge,it is much easier for modeling compared with other existing literatures.
基金The Foundation of State Key Laboratory of Widebandgap Semiconductor Power Electronics Devices(No.2017KF003)the Fundamental Research Funds for the Central Universities
文摘The radiation influences on electrical parameters of4H-SiC vertical double-implanted metal-oxide-semiconductor field effect transistor( VDMOS) are studied. By simulations on SRIM software and SILVACO software, the electrical parameters shifts of the device with defects in different regions are observed. The results indicate that the defects in different regions induced by radiations lead to different degradations of the electrical parameters. Non-ionization bulk defects in the JFET region make the drain-source on-state resistance Rdson increase,and those near the impact ionization center make the breakdown voltage Vbreakdownincrease. Moreover,the radiationinduced SiC/SiO2 interface defects,known as negative interface charges or positive interface charges,influence the electrical parameters significantly as well. The positive interface charges along the SiC/SiO2 interface above the channel region lead to a decrease in threshold voltage Vth,Rdsonand Vbreakdown,while positive interface charges along the Si C/Metal interface above the main junction of the terminal only leads to the decrease in Vbreakdown. The negative interface charges along the SiC/SiO2 interface above the channel region can make Vth,Rdsonand Vbreakdownincrease.
文摘The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.
基金Project supported by the National Natural Science Foundation of China(Grant No.61704019)
文摘Si p^+n junction diodes operating in the mode of avalanche breakdown are capable of emitting light in the visible range of 400-900 nm. In this study, to realize the switching speed in the GHz range, we present a transient model to shorten the carrier lifetime in the high electric field region by accumulating carriers in both p and n type regions. We also verify the optoelectronic characteristics by disclosing the related physical mechanisms behind the light emission phenomena. The emission of visible light by a monolithically integrated Si diode under the reverse bias is also discussed. The light is emitted as spatial sources by the defects located at the p-n junction of the reverse-biased diode. The influence of the defects on the electrical behavior is manifested as a current-dependent electroluminescence.
文摘This paper is devoted to temperature analysis on power RF LDMOS with different feature parameters of die thickness, pitch S length and finger width. The significance of these three parameters is determined from temperature comparison obtained by 3D Silvaco-Atlas device simulator. The first three simulations focus on temperature variation with the three factors at different output power density respectively. The results indicate that both the thinner die thickness and the broaden pitch S length have distinct advantages over the shorter finger width. The device, at the same time, exhibits higher temperature at a larger output power density. Simulations are further carried out on structure with combination of different pitch s length and die thickness at a large 1W/mm output power density and the temperature reduction reaches as high as 55%.
文摘The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface （VPI） and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.
文摘A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt.In addition,a differential noise cancellation circuit is proposed to enhance the noise immunity further.Meanwhile,the negative V_S capacity is improved by unifying the detected reference voltage and the logic block＇s threshold voltage.A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.
基金supported by the National Natural Science Foundation of China(Nos.BK20150627,61674030)the Natural Science Foundation of Jiangsu Province(No.61504025)the National Key research and Development Plan(No.2017YFB0402900)
文摘A high-order curvature-compensated CMOS bandgap reference（BGR） topology with a low temperature coefficient（TC） over a wide temperature range and a high power supply reject ratio（PSRR） is presented.High-order correction is realized by incorporating a nonlinear current INL, which is generated by ？V_（GS） across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of0.19 ppm/°C over the temperature range of 165 °C（-40 to 125 °C）, PSRR of-123 d B @ DC and-56 d B @ 100 k Hz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.
基金Project supported by the Natural Science Foundation of Jiangsu Province (No.BK2011059)the Program for New Century Excellent Talent in University (No.NCET-10-0331)
文摘The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.
基金Project supported by the Natural Science Foundation of Jiangsu,China(No.BK2011059)the Program for New Century Excellent Talents in University(NCET- 10-0331)the Qing Lan Project
文摘A fully integrated soft-start circuit for DC-DC buck converters is presented. The proposed high speed soft-start circuit is made of two sections： an overshoot suppression circuit and an inrush current suppression circuit. The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DC-DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13 um CMOS process. Experimental results show that the proposed high speed soft-start circuit has achieved less than 50 us start-up time. The inductor current and the output voltage increase smoothly over the whole load range.
基金supported by the Jiangsu Provincial Natural Science Fund(No.BK2012559)
文摘We present a novel gated operation active quenching circuit （AQC）. In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I-V characteristic measurement resuits of the detector. The circuit integrated with a ROIC （readout integrated circuit） is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications.
基金Project supported by the Natural Science Foundation of Jiangsu Province,China(Nos.BK2010167,BK2011059)the Program for New Century Excellent Talents in University,China(No.NCET-10-0331)the Qing Lan Project
文摘A novel digital control algorithm for digital control power factor correction is presented, which is called the prediction algorithm and has a feature of a higher PF （power factor） with lower total harmonic distortion, and a faster dynamic response with the change of the input voltage or load current. For a certain system, based on the current system state parameters, the prediction algorithm can estimate the track of the output voltage and the inductor current at the next switching cycle and get a set of optimized control sequences to perfectly track the trajectory of input voltage. The proposed prediction algorithm is verified at different conditions, and computer simulation and experimental results under multi-situations confirm the effectiveness of the prediction algorithm. Under the circumstances that the input voltage is in the range of 90-265 V and the load current in the range of 20%-100%, the PF value is larger than 0.998. The 0.02 s without overshoot. The experimental results startup and the recovery times respectively are about 0.1 s and also verify the validity of the proposed method.
基金Project supported by the Natural Science Foundation of Jiangsu Province,China(NoBK2008287)the Advanced Research of National Natural Science Foundation of Southeast University,China(NoXJ2008312)
文摘A sub-circuit SPICE model of a MOSFET for low temperature operation is presented.Two resistors are introduced for the freeze-out effect,and the explicit behavioral models are developed for them.The model can be used in a wide temperature range covering both cryogenic temperature and regular temperatures.
文摘A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabricated in an SMIC 0.13 μm CMOS process with only MOS transistors and resistors. The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from -20 to 120 ℃C. The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8 μA at room temperature. The occupied area is only 0.019 mm^2.
文摘The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons： one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon comer of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon comers at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry＇s 0.5-μm HV SOI technology.
基金Project supported by the National Natural Science Foundation of China(Nos.61274022,61201034)the Natural Science Foundation of the Jiangsu Province(No.BK2011059)+1 种基金the Program for New Century Excellent Talents in University(No.NCET-10-0331)the Qing Lan Project
文摘The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC-DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC-DC with the proposed prediction is about 8/μs when the load current changes from 0.6 to 0.1A.
