We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of t...We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.展开更多
The effect of annealing on vertically aligned TiO2 NWs deposited by glancing angle deposition（GLAD）method on Si substrate using pressed and sintered TiO2 pellets as source material is studied.The FE-SEM images revea...The effect of annealing on vertically aligned TiO2 NWs deposited by glancing angle deposition（GLAD）method on Si substrate using pressed and sintered TiO2 pellets as source material is studied.The FE-SEM images reveal the retention of vertically aligned NWs on Si substrate after annealing process.The EDS analysis of TiO2NWs sample annealed at 600 ℃ in air for 1 h shows the higher weight percentage ratio of ～2.6（i.e.,72.27%oxygen and 27.73%titanium）.The XRD pattern reveals that the polycrystalline nature of anatase TiO2 dominates the annealed NWs sample.The electrical characteristics of Al/TiO2-NWs/TiO2-TF/p-Si（NW device） and Al/TiO2-TF/p-Si（TF device） based on annealed samples are compared.It is riveting to observe a lower leakage current of ～1.32 × 10^-7 A/cm^2 at ＋1 V with interface trap density of-6.71 × 10^11eV^-1cm^-2 in NW device compared to ～2.23 × 10^-2 A/cm^2 in TF device.The dominant leakage mechanism is investigated to be generally Schottky emission;however Poole-Frenkel emission also takes place during high reverse bias beyond 4 V for NWs and 3 V for TF device.展开更多
This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology pa...This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.展开更多
基金Project supported by the Special Man-Power Development Programme in VLSI & Related Software,Phase-Ⅱ(SMDP-Ⅱ),Ministry of Information Technology,Government of Indiathe JUET,Guna(M.P.)
文摘We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.
文摘The effect of annealing on vertically aligned TiO2 NWs deposited by glancing angle deposition（GLAD）method on Si substrate using pressed and sintered TiO2 pellets as source material is studied.The FE-SEM images reveal the retention of vertically aligned NWs on Si substrate after annealing process.The EDS analysis of TiO2NWs sample annealed at 600 ℃ in air for 1 h shows the higher weight percentage ratio of ～2.6（i.e.,72.27%oxygen and 27.73%titanium）.The XRD pattern reveals that the polycrystalline nature of anatase TiO2 dominates the annealed NWs sample.The electrical characteristics of Al/TiO2-NWs/TiO2-TF/p-Si（NW device） and Al/TiO2-TF/p-Si（TF device） based on annealed samples are compared.It is riveting to observe a lower leakage current of ～1.32 × 10^-7 A/cm^2 at ＋1 V with interface trap density of-6.71 × 10^11eV^-1cm^-2 in NW device compared to ～2.23 × 10^-2 A/cm^2 in TF device.The dominant leakage mechanism is investigated to be generally Schottky emission;however Poole-Frenkel emission also takes place during high reverse bias beyond 4 V for NWs and 3 V for TF device.
基金supported by the Project SMDP-II,MCIT,Govt.of India
文摘This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.
