Soft electronics,which are designed to function under mechanical deformation(such as bending,stretching,and folding),have become essential in applications like wearable electronics,artificial skin,and brain-machine in...Soft electronics,which are designed to function under mechanical deformation(such as bending,stretching,and folding),have become essential in applications like wearable electronics,artificial skin,and brain-machine interfaces.Crystalline silicon is one of the most mature and reliable materials for high-performance electronics;however,its intrinsic brittleness and rigidity pose challenges for integrating it into soft electronics.Recent research has focused on overcoming these limitations by utilizing structural design techniques to impart flexibility and stretchability to Si-based materials,such as transforming them into thin nanomembranes or nanowires.This review summarizes key strategies in geometry engineering for integrating crystalline silicon into soft electronics,from the use of hard silicon islands to creating out-of-plane foldable silicon nanofilms on flexible substrates,and ultimately to shaping silicon nanowires using vapor-liquid-solid or in-plane solid-liquid-solid techniques.We explore the latest developments in Si-based soft electronic devices,with applications in sensors,nanoprobes,robotics,and brain-machine interfaces.Finally,the paper discusses the current challenges in the field and outlines future research directions to enable the widespread adoption of silicon-based flexible electronics.展开更多
For the characteristics of intra prediction algorithms, the data dependence and parallelism between intra prediction models are first analyzed. This paper proposes a parallelization method based on dynamic reconfigura...For the characteristics of intra prediction algorithms, the data dependence and parallelism between intra prediction models are first analyzed. This paper proposes a parallelization method based on dynamic reconfigurable array processors provided by the project team, and uses data level parallel(DLP) algorithms in multi-core units. The experimental results show that Y-component of peak signal to noise ratio(Y-PSNR) is improved about 10 dB and the time is saved 63% compared with high-efficiency video coding(HEVC) test model HM10.0. This method can effectively reduce codec time of the video and reduce computational complexity.展开更多
Aiming at the high computational complexity and low efficiency of the advanced residual prediction(ARP)algorithm in 3 dimension high-efficiency video coding(3D-HEVC),the relationship between the depth value and ARP is...Aiming at the high computational complexity and low efficiency of the advanced residual prediction(ARP)algorithm in 3 dimension high-efficiency video coding(3D-HEVC),the relationship between the depth value and ARP is analyzed.A fast ARP algorithm based on the depth value is proposed,which is implemented on the reconfigurable array processor developed by the project team.It uses a reconfigurable method to realize flexible switching between interview-ARP and tem-poral ARP.Experimental results show that while keeping the coding rate and the peak signal-to-noise ratio(PSNR)basically unchanged,the coding time of the six test sequences is reduced by 16.21%on average compared with HTM16.1.In contrast with non-reconfiguration,the average coding time is reduced by 52%,so the computational efficiency is improved.展开更多
A new set of technique was adopted in bonding Si-Si by using Ge (Ⅳ element),which is used as the substitute for the common hydrophilic method. The bond layer has no holes, and the edge bond-rate amounts to above 98%,...A new set of technique was adopted in bonding Si-Si by using Ge (Ⅳ element),which is used as the substitute for the common hydrophilic method. The bond layer has no holes, and the edge bond-rate amounts to above 98%, and the bond strength is above 2156 Pa. By doping the same kind of dopant with low-resistance in Ge, the stress compensation was realized.展开更多
When SiC MOSFET power devices operate under radiation environment conditions,radiation induces trap charges in their gate oxide,which affects the device's short-circuit and avalanche characteristics.The short-circ...When SiC MOSFET power devices operate under radiation environment conditions,radiation induces trap charges in their gate oxide,which affects the device's short-circuit and avalanche characteristics.The short-circuit and avalanche characteristics are crucial for the reliable operation of devices under radiation environments.To ensure the efficient and stable operation of SiC MOSFET power devices under radiation environments,this paper focuses on studying the degradation patterns of the short-circuit and avalanche characteristics of SiC MOSFET power devices after being subjected to radiation,and analyzes the degradation mechanisms through theory and simulation.展开更多
The evolution of chip architecture is discussed in this paper. Then MPP SoC architectures according to three kinds of computing paradigms are analyzed. Based on these discussions and analyses, array processor architec...The evolution of chip architecture is discussed in this paper. Then MPP SoC architectures according to three kinds of computing paradigms are analyzed. Based on these discussions and analyses, array processor architecture for unified change is presented, which could implement the simplification, effectiveness and versatility of both data level and non-data level parallel algorithm＇s programming.展开更多
The analytical model of voltage-controlled MOS capacitance of tapered through silicon via （TSV） is derived. To capture the frequency-dependent behavior of tapered TSV, the conventional analytical equations of RLCG f...The analytical model of voltage-controlled MOS capacitance of tapered through silicon via （TSV） is derived. To capture the frequency-dependent behavior of tapered TSV, the conventional analytical equations of RLCG for two-wire transmission lines are revised. With the adoption of MOS capacitance model and the revised RLCG analytical equations, a transmission line-type electrical model for tapered TSV is proposed finally. All the proposed models are validated by simulation tools, and a good correlation is obtained between the proposed models and simulations up to 100 GHz. With the proposed model, both the semiconductor phenomenon and frequency- dependent behavior of tapered TSV can be fully captured at high frequency, and the performance of tapered TSV can be evaluated accurately and conveniently prior to 3D IC design.展开更多
An instruction level parallel computing paradigm and a unified architecture for an array processor(AP) on a chip(SoC) are presented in this paper.Here "APU SoC" is short for "an AP SoC for the unified a...An instruction level parallel computing paradigm and a unified architecture for an array processor(AP) on a chip(SoC) are presented in this paper.Here "APU SoC" is short for "an AP SoC for the unified architecture".The MISD/MIMD architecture for instruction level parallel computing is unified with the SIMD architecture for data level parallel computing.As a result,all the computing can be implemented on an APU SoC.The APU SoC offers the rationale of an array structure for development in current technology,yet simplicity for the hardware(chip) and software(program) parallel designs.Just as a single processor chip can replace many function module chips,the APU SoC can replace the single-core/multi-core/many-core CPU chip for TLP computing and the ASIC/ASSP/FPGA/RC device array chip for Operation Level Parallel computing.展开更多
Perovskite quantum dots(PeQDs)endowed with capping ligands exhibit impressive optoelectronic properties and enable for costefficient solution processing and exciting application opportunities.We synthesize and charact...Perovskite quantum dots(PeQDs)endowed with capping ligands exhibit impressive optoelectronic properties and enable for costefficient solution processing and exciting application opportunities.We synthesize and characterize three different PeQDs with the same cubic CsPbBr_(3)core,but which are distinguished by the ligand composition and density.PeQD-1 features a binary didodecyldimethylammonium bromide(DDAB)and octanoic acid capping ligand system,with a high surface density of 1.53 nm^(-2),whereas PeQD-2 and PeQD-3 are coated by solely DDAB at a gradually lower surface density.We show that PeQD-1 endowed with highest ligand density features the highest dispersibility in toluene of 150 g/L,the highest photoluminescence quantum yield of 95%in dilute solution and 59%in a neat film,and the largest core-to-core spacing in neat thin films.We further establish that ions are released from the core of PeQD-1 when it is exposed to an electric field,although it comprises a dense coating of one capping ligand per four surface core atoms.We finally exploit these combined findings to the development of a light-emitting electrochemical cell(LEC),where the active layer is composed solely of solution-processed pure PeQDs,without additional electrolytes.In this device,the ion release is utilized as an advantage for the electrochemical doping process and efficient emissive operation of the LEC.展开更多
This paper is concerned with the design of an inference microprocessor for production rule systems. Its implementation is based on both exact and inexact (fuzzy logic) reasoning,so it can he used for building various ...This paper is concerned with the design of an inference microprocessor for production rule systems. Its implementation is based on both exact and inexact (fuzzy logic) reasoning,so it can he used for building various production rule systems.The methods of translating linguistically expressed rules into nu- merical representations are described and the hardware implementations are discussed.Finally,a parallel architecture for the inference microprocessor is presented.展开更多
基金the National Natural Science Foundation of China under granted No.62104100National Key Research Program of China under No.92164201+1 种基金National Natural Science Foundation of China for Distinguished Young Scholars under No.62325403National Natural Science Foundation of China under No.61934004.
文摘Soft electronics,which are designed to function under mechanical deformation(such as bending,stretching,and folding),have become essential in applications like wearable electronics,artificial skin,and brain-machine interfaces.Crystalline silicon is one of the most mature and reliable materials for high-performance electronics;however,its intrinsic brittleness and rigidity pose challenges for integrating it into soft electronics.Recent research has focused on overcoming these limitations by utilizing structural design techniques to impart flexibility and stretchability to Si-based materials,such as transforming them into thin nanomembranes or nanowires.This review summarizes key strategies in geometry engineering for integrating crystalline silicon into soft electronics,from the use of hard silicon islands to creating out-of-plane foldable silicon nanofilms on flexible substrates,and ultimately to shaping silicon nanowires using vapor-liquid-solid or in-plane solid-liquid-solid techniques.We explore the latest developments in Si-based soft electronic devices,with applications in sensors,nanoprobes,robotics,and brain-machine interfaces.Finally,the paper discusses the current challenges in the field and outlines future research directions to enable the widespread adoption of silicon-based flexible electronics.
基金Supported by the National Natural Science Foundation of China(No.61772417,61634004,61602377,61272120)the Shaanxi Provincial Co-ordination Innovation Project of Science and Technology(No.2016KTZDGY02-04-02)the Shaanxi Provincial key R&D plan(No.2017GY-060)
文摘For the characteristics of intra prediction algorithms, the data dependence and parallelism between intra prediction models are first analyzed. This paper proposes a parallelization method based on dynamic reconfigurable array processors provided by the project team, and uses data level parallel(DLP) algorithms in multi-core units. The experimental results show that Y-component of peak signal to noise ratio(Y-PSNR) is improved about 10 dB and the time is saved 63% compared with high-efficiency video coding(HEVC) test model HM10.0. This method can effectively reduce codec time of the video and reduce computational complexity.
基金the National Natural Science Foundation of China(No.61834005,61772417,61634004,61602377)the Shaanxi Provincial Co-ordination Innovation Project of Science and Technology(No.2016KTZDGY02-04-02)。
文摘Aiming at the high computational complexity and low efficiency of the advanced residual prediction(ARP)algorithm in 3 dimension high-efficiency video coding(3D-HEVC),the relationship between the depth value and ARP is analyzed.A fast ARP algorithm based on the depth value is proposed,which is implemented on the reconfigurable array processor developed by the project team.It uses a reconfigurable method to realize flexible switching between interview-ARP and tem-poral ARP.Experimental results show that while keeping the coding rate and the peak signal-to-noise ratio(PSNR)basically unchanged,the coding time of the six test sequences is reduced by 16.21%on average compared with HTM16.1.In contrast with non-reconfiguration,the average coding time is reduced by 52%,so the computational efficiency is improved.
文摘A new set of technique was adopted in bonding Si-Si by using Ge (Ⅳ element),which is used as the substitute for the common hydrophilic method. The bond layer has no holes, and the edge bond-rate amounts to above 98%, and the bond strength is above 2156 Pa. By doping the same kind of dopant with low-resistance in Ge, the stress compensation was realized.
文摘When SiC MOSFET power devices operate under radiation environment conditions,radiation induces trap charges in their gate oxide,which affects the device's short-circuit and avalanche characteristics.The short-circuit and avalanche characteristics are crucial for the reliable operation of devices under radiation environments.To ensure the efficient and stable operation of SiC MOSFET power devices under radiation environments,this paper focuses on studying the degradation patterns of the short-circuit and avalanche characteristics of SiC MOSFET power devices after being subjected to radiation,and analyzes the degradation mechanisms through theory and simulation.
文摘The evolution of chip architecture is discussed in this paper. Then MPP SoC architectures according to three kinds of computing paradigms are analyzed. Based on these discussions and analyses, array processor architecture for unified change is presented, which could implement the simplification, effectiveness and versatility of both data level and non-data level parallel algorithm＇s programming.
基金Project supported by the National Defense Basic Scientific Research Program of China(No.A0320132012)
文摘The analytical model of voltage-controlled MOS capacitance of tapered through silicon via （TSV） is derived. To capture the frequency-dependent behavior of tapered TSV, the conventional analytical equations of RLCG for two-wire transmission lines are revised. With the adoption of MOS capacitance model and the revised RLCG analytical equations, a transmission line-type electrical model for tapered TSV is proposed finally. All the proposed models are validated by simulation tools, and a good correlation is obtained between the proposed models and simulations up to 100 GHz. With the proposed model, both the semiconductor phenomenon and frequency- dependent behavior of tapered TSV can be fully captured at high frequency, and the performance of tapered TSV can be evaluated accurately and conveniently prior to 3D IC design.
文摘An instruction level parallel computing paradigm and a unified architecture for an array processor(AP) on a chip(SoC) are presented in this paper.Here "APU SoC" is short for "an AP SoC for the unified architecture".The MISD/MIMD architecture for instruction level parallel computing is unified with the SIMD architecture for data level parallel computing.As a result,all the computing can be implemented on an APU SoC.The APU SoC offers the rationale of an array structure for development in current technology,yet simplicity for the hardware(chip) and software(program) parallel designs.Just as a single processor chip can replace many function module chips,the APU SoC can replace the single-core/multi-core/many-core CPU chip for TLP computing and the ASIC/ASSP/FPGA/RC device array chip for Operation Level Parallel computing.
基金The authors acknowledge generous support from J.C.Kempes Minnes Stipendiefond(No.SMK-1849.1,21-0015)the Swedish Energy Agency(Nos.45419-1,46523-1,and 50779-1)+4 种基金the Swedish Research Council(Nos.2018-03937,2019-02345,and 2020-04437)the Swedish Foundation for Strategic Research,Stiftelsen Olle Engkvist Byggmästare(Nos.186-0637 and 193-0578)Bertil&Britt Svenssons stiftelse för belysningsteknik,the Swedish Foundation for International Cooperation in Research,Higher Education via an Initiation Grant for Internationalization(No.2019-8553)Innovation Technology Platform Project Jointly Built by Yangzhou City and Yangzhou University,China(No.YZ2020268)Jiangsu Students’Innovation and Entrepreneurship Training Program(No.202211117040Z).
文摘Perovskite quantum dots(PeQDs)endowed with capping ligands exhibit impressive optoelectronic properties and enable for costefficient solution processing and exciting application opportunities.We synthesize and characterize three different PeQDs with the same cubic CsPbBr_(3)core,but which are distinguished by the ligand composition and density.PeQD-1 features a binary didodecyldimethylammonium bromide(DDAB)and octanoic acid capping ligand system,with a high surface density of 1.53 nm^(-2),whereas PeQD-2 and PeQD-3 are coated by solely DDAB at a gradually lower surface density.We show that PeQD-1 endowed with highest ligand density features the highest dispersibility in toluene of 150 g/L,the highest photoluminescence quantum yield of 95%in dilute solution and 59%in a neat film,and the largest core-to-core spacing in neat thin films.We further establish that ions are released from the core of PeQD-1 when it is exposed to an electric field,although it comprises a dense coating of one capping ligand per four surface core atoms.We finally exploit these combined findings to the development of a light-emitting electrochemical cell(LEC),where the active layer is composed solely of solution-processed pure PeQDs,without additional electrolytes.In this device,the ion release is utilized as an advantage for the electrochemical doping process and efficient emissive operation of the LEC.
文摘This paper is concerned with the design of an inference microprocessor for production rule systems. Its implementation is based on both exact and inexact (fuzzy logic) reasoning,so it can he used for building various production rule systems.The methods of translating linguistically expressed rules into nu- merical representations are described and the hardware implementations are discussed.Finally,a parallel architecture for the inference microprocessor is presented.
