In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metal...In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 gm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.展开更多
Thermochemical heat storage is a promising technology for improving thermal energy efficiency. To investigate the durability of the CaO/Ca(OH)2 reaction and develop a reactivation method, repetitive charging/dischargi...Thermochemical heat storage is a promising technology for improving thermal energy efficiency. To investigate the durability of the CaO/Ca(OH)2 reaction and develop a reactivation method, repetitive charging/discharging operation of a packed bed reactor with a thick packed bed was conducted, and variations in the discharging behavior, final conversion, and reactant activity were investigated. Owing to the formation of a deactivated sintered reactant block, the discharging time halved and the final conversion ratio decreased by the 53rd discharging operation. To enhance durability, a reactivation method using high-pressure vapor was implemented during the 54th discharging operation. Following reactivation, the final conversion increased 15%, and the discharging time tripled when compared with the discharging operation before reactivation, confirming the success of this simple reactivation method.展开更多
Large amounts of waste heat below 100oC from the industrial sector are re-leased into the atmosphere. It has been suggested that energy system efficiency can be increased with adsorption chillers. However, the cooling...Large amounts of waste heat below 100oC from the industrial sector are re-leased into the atmosphere. It has been suggested that energy system efficiency can be increased with adsorption chillers. However, the cooling power and coefficient of performance (COP) of conventional adsorption chillers significantly decrease with the desorption temperature. In this paper, we proposed a mechanical booster pump (MBP)-assisted adsorption chiller cycle, and evaluated its performances. In the cycle, a MBP was incorporated into a zeolite-water-type adsorption chiller for facilitating water vapor transportation between an adsorber and an evaporator/condenser. We have experimentally studied the effect of the input electrical power of MBP on the performances of adsorption chiller cycle. It has been demonstrated that the heat input achieved by using MBP at the desorption temperature of 50oC was 1.6 times higher than that of without MBP at the desorption temperature of 60oC. And the increase of pump power was found to be effective in increasing the heat input. Therefore, it was confirmed that the operation range of desorption temperature, which can be generated by using the waste heat, was extended and the cooling power was increased directly by using MBP.展开更多
A low voltage low power CMOS limiter and received signal strength indicator(RSSI) with an integrated automatic gain control(AGC) loop for a short-distance receiver are implemented in SMIC 0.13μm CMOS technology.The R...A low voltage low power CMOS limiter and received signal strength indicator(RSSI) with an integrated automatic gain control(AGC) loop for a short-distance receiver are implemented in SMIC 0.13μm CMOS technology.The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within i0.5 dB for an input power from -65 to -8 dBm.The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA(I and Q paths) from a 1.2 V supply.Auto LNA gain mode selection with a combined RSSI function is also presented.Furthermore,with the compensation circuit,the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.展开更多
A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-sou...A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μm CMOS technology, it occupies a 0.612 mm^2 die size.展开更多
Methicillin-resistant Staphylococcus aureus(MRSA) causes widespread infections and poses serious public health concerns. Its high level of resistance to multiple antibiotics has garnered growing interest in identifyin...Methicillin-resistant Staphylococcus aureus(MRSA) causes widespread infections and poses serious public health concerns. Its high level of resistance to multiple antibiotics has garnered growing interest in identifying and applying novel antibacterial compounds derived from natural sources. In this study, we purified a biosurfactant(BS) from Bacillus rugosus HH2 to develop a natural antibacterial agent. This agent was then reinforced with chitooligosaccharide(COS) and polyvinyl alcohol(PVA) to create a hydrogel that promoted healing in MRSA-infected wounds. The COS/PVA/BS hydrogel was readily fabricated via the freeze-thaw method and demonstrated excellent mechanical strength, biological activity,and biocompatibility. In vitro assays confirmed that the hydrogel significantly enhanced the proliferation, migration, angiogenesis, and extracellular matrix deposition of fibroblasts,keratinocytes, and endothelial cells. Moreover, it exhibited strong bacteriostatic and bactericidal activities against MRSA, along with potent antibiofilm activity and inhibition of virulence factors relevant to MRSA-induced wound infections. Its anti-virulence effects have been linked to the downregulation of quorum sensing and virulence-related genes in MRSA. In an in vivo model of MRSA-induced infection, the COS/PVA/BS hydrogel significantly accelerated wound healing and markedly reduced the MRSA burden. Immunofluorescence staining confirmed enhanced neovascularization and regulated macrophage responses,underscoring the angiogenic and immunomodulatory effects of the hydrogel. Overall,the COS/PVA/BS hydrogel represents a promising therapeutic strategy for addressing antibiotic-resistant bacterial infections and promoting wound repair, supported by the use of common raw materials, a simple fabrication process, and high-yield production of natural antibacterial agents.展开更多
A novel I/Q mismatch calibration technique based on a digital baseband for a direct conversion transmitter is implemented in TSMC 0.13μm CMOS technology.The proposed technique finishes a calibration task, which only ...A novel I/Q mismatch calibration technique based on a digital baseband for a direct conversion transmitter is implemented in TSMC 0.13μm CMOS technology.The proposed technique finishes a calibration task, which only needs a calibration chain to detect mismatches and then transmit them to the digital baseband.Simulation results show that the calibrated errors of the proposed technique are less than 7%.The measurement results indicate the function of the proposed technique is correct,but the performance should be improved further.展开更多
A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including ...A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA（RXPGA） provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA（TXPGA） covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA （I and Q path） under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC（DC offset cancellation） circuit shows 10 kHz of HPCF（high pass cutoff frequency） and the DCOC settling time is less than 0.45μs.展开更多
A low voltage,highly linear transconductance-C（G_m-C） low-pass filter for wireless local area network （WLAN） transceiver application is proposed.This transmitter（Tx） filter adopts a 9.8 MHz 3rd-order Chebyshev l...A low voltage,highly linear transconductance-C（G_m-C） low-pass filter for wireless local area network （WLAN） transceiver application is proposed.This transmitter（Tx） filter adopts a 9.8 MHz 3rd-order Chebyshev low pass prototype and achieves 35 dB stop-band attenuation at 30 MHz frequency.By utilizing pseudo-differential linear-region MOS transconductors,the filter IIP_3 is measured to be as high as 9.5 dBm.Fabricated in a 0.35μm standard CMOS technology,the proposed filter chip occupies a 0.41×0.17 mm^2 die area and consumes 3.36 mA from a 3.3-V power supply.展开更多
A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linea...A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linear gain is controlled by the charge pump.The AGC was implemented in a 0.18μm CMOS technology.The dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain ranges.It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.展开更多
A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die a...A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 ×0.419 mm^2.展开更多
A low power process/temperature variation-tolerant CMOS received signal strength indicator （RSSI） and limiter amplifier are designed using SMIC 0.13 μm CMOS technology. The limiter uses six-stage amplifier architec...A low power process/temperature variation-tolerant CMOS received signal strength indicator （RSSI） and limiter amplifier are designed using SMIC 0.13 μm CMOS technology. The limiter uses six-stage amplifier architecture for minimum power consideration. The RSSI has a dynamic range of more than 60 dB, and the RSSI linearity error is within 4-0.5 dB for an input power from -65 to -8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature independence and robustness against process variation characteristics. The RSSI with an integrated AGC loop draws 1.5 mA （I and Q paths） from a 1.2 V single supply.展开更多
An asymmetric MOSFET-C band-pass filter （BPF） with on chip charge pump auto-tuning is presented. It is implemented in UMC （United Manufacturing Corporation） 0.18 μm CMOS process technology. The filter system with...An asymmetric MOSFET-C band-pass filter （BPF） with on chip charge pump auto-tuning is presented. It is implemented in UMC （United Manufacturing Corporation） 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point （ⅡP3） is 16.621 dBm, with 50Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS （global positioning system） and Bluetooth systems.展开更多
This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, whic...This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 x 550 μm^2 and the quiescent current is 130 μA.展开更多
A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based techniqu...A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.展开更多
基金Project supported by the Key Program of the National Natural Science Foundation of China (Grant No. 61036004)the Shenzhen Science & Technology Foundation, China (Grant No. CXB201005250031A)+1 种基金the Fundamental Research Project of Shenzhen Science & Technology Foundation, China (Grant No. JC201005280670A)the International Collaboration Project of Shenzhen Science & Technology Foundation, China (Grant No. ZYA2010006030006A)
文摘In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 gm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.
文摘Thermochemical heat storage is a promising technology for improving thermal energy efficiency. To investigate the durability of the CaO/Ca(OH)2 reaction and develop a reactivation method, repetitive charging/discharging operation of a packed bed reactor with a thick packed bed was conducted, and variations in the discharging behavior, final conversion, and reactant activity were investigated. Owing to the formation of a deactivated sintered reactant block, the discharging time halved and the final conversion ratio decreased by the 53rd discharging operation. To enhance durability, a reactivation method using high-pressure vapor was implemented during the 54th discharging operation. Following reactivation, the final conversion increased 15%, and the discharging time tripled when compared with the discharging operation before reactivation, confirming the success of this simple reactivation method.
文摘Large amounts of waste heat below 100oC from the industrial sector are re-leased into the atmosphere. It has been suggested that energy system efficiency can be increased with adsorption chillers. However, the cooling power and coefficient of performance (COP) of conventional adsorption chillers significantly decrease with the desorption temperature. In this paper, we proposed a mechanical booster pump (MBP)-assisted adsorption chiller cycle, and evaluated its performances. In the cycle, a MBP was incorporated into a zeolite-water-type adsorption chiller for facilitating water vapor transportation between an adsorber and an evaporator/condenser. We have experimentally studied the effect of the input electrical power of MBP on the performances of adsorption chiller cycle. It has been demonstrated that the heat input achieved by using MBP at the desorption temperature of 50oC was 1.6 times higher than that of without MBP at the desorption temperature of 60oC. And the increase of pump power was found to be effective in increasing the heat input. Therefore, it was confirmed that the operation range of desorption temperature, which can be generated by using the waste heat, was extended and the cooling power was increased directly by using MBP.
基金supported by the Doctoral Scientific Starting Research from the Xi'an Polytechnic University,Chinathe Doctoral Scientific Starting Research from the Xi'an Polytechnic University(No.BS1209)
文摘A low voltage low power CMOS limiter and received signal strength indicator(RSSI) with an integrated automatic gain control(AGC) loop for a short-distance receiver are implemented in SMIC 0.13μm CMOS technology.The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within i0.5 dB for an input power from -65 to -8 dBm.The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA(I and Q paths) from a 1.2 V supply.Auto LNA gain mode selection with a combined RSSI function is also presented.Furthermore,with the compensation circuit,the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.
文摘A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μm CMOS technology, it occupies a 0.612 mm^2 die size.
基金supported by the Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education (RS-2021-NR060118,RS-2024-00408404, and RS-2025-00555808)supported by the Korea Institute of Marine Science&Technology Promotion (KIMST)funded by the Ministry of Oceans and Fisheries (RS-2024-00404977)。
文摘Methicillin-resistant Staphylococcus aureus(MRSA) causes widespread infections and poses serious public health concerns. Its high level of resistance to multiple antibiotics has garnered growing interest in identifying and applying novel antibacterial compounds derived from natural sources. In this study, we purified a biosurfactant(BS) from Bacillus rugosus HH2 to develop a natural antibacterial agent. This agent was then reinforced with chitooligosaccharide(COS) and polyvinyl alcohol(PVA) to create a hydrogel that promoted healing in MRSA-infected wounds. The COS/PVA/BS hydrogel was readily fabricated via the freeze-thaw method and demonstrated excellent mechanical strength, biological activity,and biocompatibility. In vitro assays confirmed that the hydrogel significantly enhanced the proliferation, migration, angiogenesis, and extracellular matrix deposition of fibroblasts,keratinocytes, and endothelial cells. Moreover, it exhibited strong bacteriostatic and bactericidal activities against MRSA, along with potent antibiofilm activity and inhibition of virulence factors relevant to MRSA-induced wound infections. Its anti-virulence effects have been linked to the downregulation of quorum sensing and virulence-related genes in MRSA. In an in vivo model of MRSA-induced infection, the COS/PVA/BS hydrogel significantly accelerated wound healing and markedly reduced the MRSA burden. Immunofluorescence staining confirmed enhanced neovascularization and regulated macrophage responses,underscoring the angiogenic and immunomodulatory effects of the hydrogel. Overall,the COS/PVA/BS hydrogel represents a promising therapeutic strategy for addressing antibiotic-resistant bacterial infections and promoting wound repair, supported by the use of common raw materials, a simple fabrication process, and high-yield production of natural antibacterial agents.
基金Project supported by the Doctoral Scientific Starting Research from the Xi'an Polytechnic University(No.BS1209)the Shaanxi Provincial Education Department(No.12JK0546)
文摘A novel I/Q mismatch calibration technique based on a digital baseband for a direct conversion transmitter is implemented in TSMC 0.13μm CMOS technology.The proposed technique finishes a calibration task, which only needs a calibration chain to detect mismatches and then transmit them to the digital baseband.Simulation results show that the calibrated errors of the proposed technique are less than 7%.The measurement results indicate the function of the proposed technique is correct,but the performance should be improved further.
文摘A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA（RXPGA） provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA（TXPGA） covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA （I and Q path） under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC（DC offset cancellation） circuit shows 10 kHz of HPCF（high pass cutoff frequency） and the DCOC settling time is less than 0.45μs.
文摘A low voltage,highly linear transconductance-C（G_m-C） low-pass filter for wireless local area network （WLAN） transceiver application is proposed.This transmitter（Tx） filter adopts a 9.8 MHz 3rd-order Chebyshev low pass prototype and achieves 35 dB stop-band attenuation at 30 MHz frequency.By utilizing pseudo-differential linear-region MOS transconductors,the filter IIP_3 is measured to be as high as 9.5 dBm.Fabricated in a 0.35μm standard CMOS technology,the proposed filter chip occupies a 0.41×0.17 mm^2 die area and consumes 3.36 mA from a 3.3-V power supply.
文摘A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linear gain is controlled by the charge pump.The AGC was implemented in a 0.18μm CMOS technology.The dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain ranges.It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.
文摘A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 ×0.419 mm^2.
基金Project supported by the Doctoral Scientific Starting Research from the Xi'an Polytechnic University
文摘A low power process/temperature variation-tolerant CMOS received signal strength indicator （RSSI） and limiter amplifier are designed using SMIC 0.13 μm CMOS technology. The limiter uses six-stage amplifier architecture for minimum power consideration. The RSSI has a dynamic range of more than 60 dB, and the RSSI linearity error is within 4-0.5 dB for an input power from -65 to -8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature independence and robustness against process variation characteristics. The RSSI with an integrated AGC loop draws 1.5 mA （I and Q paths） from a 1.2 V single supply.
文摘An asymmetric MOSFET-C band-pass filter （BPF） with on chip charge pump auto-tuning is presented. It is implemented in UMC （United Manufacturing Corporation） 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point （ⅡP3） is 16.621 dBm, with 50Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS （global positioning system） and Bluetooth systems.
文摘This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 x 550 μm^2 and the quiescent current is 130 μA.
文摘A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.
