A programmable transversal equalizer for electronic dispersion compensation(EDC) in optical fiber communication systems is developed.Based on the SiGe technology with a cut-off frequency of 80 GHz,the equalizer consis...A programmable transversal equalizer for electronic dispersion compensation(EDC) in optical fiber communication systems is developed.Based on the SiGe technology with a cut-off frequency of 80 GHz,the equalizer consists of 6 seriesparallel amplifiers as delay units and 7 Gilbert variable gain amplifiers as taps,which ensure that the equalizer can work at the bit rate of 10 Gb/s.With different tap gains,the forward voltage gain of the transversal equalizer varies,which demonstrates that the equalizer has various filtering characteristics such as low pass filtering,band pass filtering,band reject filtering,and notch filtering,so it can effectively simulate the inverse transfer function of dispersive channels in optical communications,and can be used for compensating the inter-symbol interference and other nonlinear problems caused by dispersion.The equalizer(including pads) occupies an area of 0.40 mm × 1.08 mm,and its total power dissipation is 400 mW with 3.3 V power supply.展开更多
A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are impleme...A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.展开更多
Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly co...Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly coupled with the CPU chips. Designing a new interconnection technology thus requires considering not only the interconnection itself, but also the design of the processors that will rely on it. In this paper, we study memory hierarchy implications for the design of high-speed datacenter interconnects particularly as they affect remote memory access -- and we use PCIe as the vehicle for our investigations. To that end, we build three complementary platforms： a PCIe-interconnected prototype server with which we measure and analyze current bottlenecks; a software simulator that lets us model microarchitectural and cache hierarchy changes; and an FPGA prototype system with a streamlined switchless customized protocol Thunder with which we study hardware optimizations outside the processor. We highlight several architectural modifications to better support remote memory access and communication, and quantify their impact and ]imitations.展开更多
基金supported by the Natural Science Foundation of Hebei Province (No.F2008000116)
文摘A programmable transversal equalizer for electronic dispersion compensation(EDC) in optical fiber communication systems is developed.Based on the SiGe technology with a cut-off frequency of 80 GHz,the equalizer consists of 6 seriesparallel amplifiers as delay units and 7 Gilbert variable gain amplifiers as taps,which ensure that the equalizer can work at the bit rate of 10 Gb/s.With different tap gains,the forward voltage gain of the transversal equalizer varies,which demonstrates that the equalizer has various filtering characteristics such as low pass filtering,band pass filtering,band reject filtering,and notch filtering,so it can effectively simulate the inverse transfer function of dispersive channels in optical communications,and can be used for compensating the inter-symbol interference and other nonlinear problems caused by dispersion.The equalizer(including pads) occupies an area of 0.40 mm × 1.08 mm,and its total power dissipation is 400 mW with 3.3 V power supply.
基金Supported by the National Natural Science Foundation of China (No.60276040).
文摘A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.
基金This work was supported by the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No. XDA06010401, and the National Natural Science Foundation of China under Grant Nos. 61100010, 61402438, and 61402439.
文摘Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly coupled with the CPU chips. Designing a new interconnection technology thus requires considering not only the interconnection itself, but also the design of the processors that will rely on it. In this paper, we study memory hierarchy implications for the design of high-speed datacenter interconnects particularly as they affect remote memory access -- and we use PCIe as the vehicle for our investigations. To that end, we build three complementary platforms： a PCIe-interconnected prototype server with which we measure and analyze current bottlenecks; a software simulator that lets us model microarchitectural and cache hierarchy changes; and an FPGA prototype system with a streamlined switchless customized protocol Thunder with which we study hardware optimizations outside the processor. We highlight several architectural modifications to better support remote memory access and communication, and quantify their impact and ]imitations.
