Conventional OFDM transmission system uses a fixed-length Cyclic Prefix to counteract Inter-Symbol Inter- ferences (ISI) caused by channel delay spreading under wireless mobile environment. This may cause considerabl...Conventional OFDM transmission system uses a fixed-length Cyclic Prefix to counteract Inter-Symbol Inter- ferences (ISI) caused by channel delay spreading under wireless mobile environment. This may cause considerable per- formance deterioration when the CP length is less than the channel RMS delay spread, or may decrease the system power and spectrum efficiency when it is much larger. A novel Orthogonal Frequency Division Multiplexing (OFDM) transmission scheme is proposed in this paper to adapt the CP length to the variation of channel delay spread. AOFDM-VCPL utilizes the preamble or pilot sub-carriers of each OFDM packet to estimate the channel RMS delay spread; and then uses a criterion to calculate the CP length , which finally affects the OFDM transmitter. As illustrated in the simulation section, by deploying this scheme in a typical wireless environment, the system can transmit at data rate 11.5 Mb/s higher than conventional non-adaptive system while gaining a 0.65 dB power saving at the same BER performance.展开更多
This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challen...This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.展开更多
基金Project supported by the National Natural Science Foundation ofChina (No. 60002003) and the Hi-Tech Research and Develop-ment Program (863) of China (No. 2002AA123044)
文摘Conventional OFDM transmission system uses a fixed-length Cyclic Prefix to counteract Inter-Symbol Inter- ferences (ISI) caused by channel delay spreading under wireless mobile environment. This may cause considerable per- formance deterioration when the CP length is less than the channel RMS delay spread, or may decrease the system power and spectrum efficiency when it is much larger. A novel Orthogonal Frequency Division Multiplexing (OFDM) transmission scheme is proposed in this paper to adapt the CP length to the variation of channel delay spread. AOFDM-VCPL utilizes the preamble or pilot sub-carriers of each OFDM packet to estimate the channel RMS delay spread; and then uses a criterion to calculate the CP length , which finally affects the OFDM transmitter. As illustrated in the simulation section, by deploying this scheme in a typical wireless environment, the system can transmit at data rate 11.5 Mb/s higher than conventional non-adaptive system while gaining a 0.65 dB power saving at the same BER performance.
文摘This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.
