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The Leakage Current Improvement of a Ni-Silicided SiGe/Si Junction Using a Si Cap Layer and the PAI Technique
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作者 CHANG Jian-Guang WU Chun-Bo +4 位作者 JI Xiao-Li MA Hao-Wen YAN Feng SHI Yi ZHANG Rong 《Chinese Physics Letters》 SCIE CAS CSCD 2012年第5期236-239,共4页
We investigate the leakage current of ultra-shallow Ni-silicided SiGe/Si junctions for 45 nm CMOS technology using a Si cap layer and the pre-amorphization implantation (PAI) process.It is found that with the conventi... We investigate the leakage current of ultra-shallow Ni-silicided SiGe/Si junctions for 45 nm CMOS technology using a Si cap layer and the pre-amorphization implantation (PAI) process.It is found that with the conventional Ni silicide method,the leakage current of a p+ (SiGe)-n(Si) junction is large and attributed to band-to-band tunneling and the generation-recombination process. The two leakage contributors can be suppressed quite effectively when a Si cap layer is added in the Ni silicide method.The leakage reduction is about one order of magnitude and could be associated with the suppression of the agglomeration of the Ni germano-silicide film.In addition,the PAI process after the application of a Si cap layer has little effect on improving the junction leakage but reduces the sheet resistance of the silicide film.As a result,the novel Ni silicide method using a Si cap combined with PAI is a promising choice for SiGe junctions in advanced technology. 展开更多
关键词 SIGE/SI IMPLANTATION LEAKAGE
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Direct Experimental Evidence of Hole Trapping in Negative Bias Temperature Instability
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作者 JI Xiao-Li LIAO Yi-Ming +3 位作者 YAN Feng SHI Yi ZHANG Guan GUO Qiang 《Chinese Physics Letters》 SCIE CAS CSCD 2011年第10期195-198,共4页
Negative bias temperature instability(NBTI)in ultrathin-plasma-nitrided-oxide(PNO)based p-type metal-oxide-semiconductor field effect transistors(pMOSFETs)is investigated at temperatures ranging from 220 K to 470 K.It... Negative bias temperature instability(NBTI)in ultrathin-plasma-nitrided-oxide(PNO)based p-type metal-oxide-semiconductor field effect transistors(pMOSFETs)is investigated at temperatures ranging from 220 K to 470 K.It is found that the threshold voltage VT degradation below 290 K is dominated by the hole trapping process.Further studies unambiguously show that this process is unnecessarily related to nitrogen but the incorporation of nitrogen in the gate dielectric increases the probability of hole trapping in the NBTI process as it introduces extra trap states located in the upper half of the Si band gap.The possible hole trapping mechanism in NBTI stressed PNO pMOSFETs is suggested by taking account of oxygen and nitrogen related trap centers. 展开更多
关键词 TRAPPING DIELECTRIC necessarily
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