This paper presents a built-in self-test (BIST) scheme for detecting allrobustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit.The test pattern generator (TPG) generates all...This paper presents a built-in self-test (BIST) scheme for detecting allrobustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit.The test pattern generator (TPG) generates all n·2~n single-input-change (SIC) ordered test pairsfor an n-input circuit-under-test (CUT) contained in a sequence of length 2n·2~n. The proposeddesign is universal, i.e., independent of the structure and functionality of the CUT. A counter thatcounts the number of alternate transitions at the output of the CUT, is used as a signatureanalyzer (SA). The design of TPG and SA is simple and no special design-or synthesis-for-testabilitytechniques and/or additional control lines are needed.展开更多
文摘This paper presents a built-in self-test (BIST) scheme for detecting allrobustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit.The test pattern generator (TPG) generates all n·2~n single-input-change (SIC) ordered test pairsfor an n-input circuit-under-test (CUT) contained in a sequence of length 2n·2~n. The proposeddesign is universal, i.e., independent of the structure and functionality of the CUT. A counter thatcounts the number of alternate transitions at the output of the CUT, is used as a signatureanalyzer (SA). The design of TPG and SA is simple and no special design-or synthesis-for-testabilitytechniques and/or additional control lines are needed.
