Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nod...Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance.In this study,for the first time,we demonstrate methods of enhancing p-channel FinFET(pFET)performance on a fully integrated advanced FinFET platform via source/drain(S/D)cavity structure optimization.By modulating the cavity depth and proximity around the optimal reference point,we show that the trade-off between the S/D resistance and short channel effect,as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization.An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.展开更多
“Industry 4.0” has become the future direction of manufacturing industry. To prepare for this upgrade, it is important to study the automation of semiconductor failure analysis. In this paper, the sample polishing a...“Industry 4.0” has become the future direction of manufacturing industry. To prepare for this upgrade, it is important to study the automation of semiconductor failure analysis. In this paper, the sample polishing activity was studied for upgrading to a smart polishing process. Two major issues were identified in implementing the smart polishing process: the optimization of current polishing recipes and the capability of making decisions based on live feedback. With the help of Solver add-in, the current polishing recipes were optimized. To make decisions based on live images captured during polishing, strategies were explored based on finger polishing process study. Our investigation showed that a grey scale line profile analysis on images can be used to build the vision capability of our smart polishing system, on which a decision- making capability can be developed.展开更多
Self-aligned multiple patterning (SAMP) can enable the semiconductor scaling before EUV lithography becomes mature for industry use.Theoretically any small size of pitch can be achieved by repeating SADP on same wafer...Self-aligned multiple patterning (SAMP) can enable the semiconductor scaling before EUV lithography becomes mature for industry use.Theoretically any small size of pitch can be achieved by repeating SADP on same wafer but with challenges of pitch walking and line cut since line cut has to be done by lithography instead of self-aligned method.Line cut can become an issue at sub-30nm pitch due to edge placement error (EPE).In this paper we will discuss some recent novel ideas on line cut after self-aligned multiple patterning.展开更多
A vectorial optical field generator(VOF-Gen) based on two reflective phase-only liquid crystal spatial light modulators enables the creation of an arbitrary optical complex field. In this work, the capabilities of the...A vectorial optical field generator(VOF-Gen) based on two reflective phase-only liquid crystal spatial light modulators enables the creation of an arbitrary optical complex field. In this work, the capabilities of the VOF-Gen in terms of manipulating the spatial distributions of phase, amplitude, and polarization are experimentally demonstrated by generating a radially polarized optical field consisted of five annular rings, the focusing properties of which are also numerically studied with vectorial diffraction theory. By carefully adjusting the relative amplitude and phase between the adjacent rings, an optical needle field with purely longitudinal polarization can be produced in the focal region of a high numerical aperture lens. The versatile method presented in this work can be easily extended to the generation of a vectorial optical field with any desired complex distributions.展开更多
文摘Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance.In this study,for the first time,we demonstrate methods of enhancing p-channel FinFET(pFET)performance on a fully integrated advanced FinFET platform via source/drain(S/D)cavity structure optimization.By modulating the cavity depth and proximity around the optimal reference point,we show that the trade-off between the S/D resistance and short channel effect,as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization.An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.
文摘“Industry 4.0” has become the future direction of manufacturing industry. To prepare for this upgrade, it is important to study the automation of semiconductor failure analysis. In this paper, the sample polishing activity was studied for upgrading to a smart polishing process. Two major issues were identified in implementing the smart polishing process: the optimization of current polishing recipes and the capability of making decisions based on live feedback. With the help of Solver add-in, the current polishing recipes were optimized. To make decisions based on live images captured during polishing, strategies were explored based on finger polishing process study. Our investigation showed that a grey scale line profile analysis on images can be used to build the vision capability of our smart polishing system, on which a decision- making capability can be developed.
文摘Self-aligned multiple patterning (SAMP) can enable the semiconductor scaling before EUV lithography becomes mature for industry use.Theoretically any small size of pitch can be achieved by repeating SADP on same wafer but with challenges of pitch walking and line cut since line cut has to be done by lithography instead of self-aligned method.Line cut can become an issue at sub-30nm pitch due to edge placement error (EPE).In this paper we will discuss some recent novel ideas on line cut after self-aligned multiple patterning.
文摘A vectorial optical field generator(VOF-Gen) based on two reflective phase-only liquid crystal spatial light modulators enables the creation of an arbitrary optical complex field. In this work, the capabilities of the VOF-Gen in terms of manipulating the spatial distributions of phase, amplitude, and polarization are experimentally demonstrated by generating a radially polarized optical field consisted of five annular rings, the focusing properties of which are also numerically studied with vectorial diffraction theory. By carefully adjusting the relative amplitude and phase between the adjacent rings, an optical needle field with purely longitudinal polarization can be produced in the focal region of a high numerical aperture lens. The versatile method presented in this work can be easily extended to the generation of a vectorial optical field with any desired complex distributions.
