This paper presents a new type of fault current limiter (FCL) based on fast closing switch, which is composed of a capacitor bank and a reactor in series. The main control component is a fast closing switch connecte...This paper presents a new type of fault current limiter (FCL) based on fast closing switch, which is composed of a capacitor bank and a reactor in series. The main control component is a fast closing switch connected in parallel with the capacitors, which is driven by the electromagnetic repulsion force. It can response the order within 1 ms. When fault occurs, the switch closes and the capacitors are bypassed, and the fault current is limited by the reactor. Simulation analysis and experiment show that the electromagnetic repulsion force actuator can meet the demand of fast closing switch, it is feasible to develop the FCL with low cost and high reliability.展开更多
This paper presents a novel framework for IP Differentiated Services (DiffServ) over optical burst switching (OBS), namely, DS-OBS. The network architecture, functional model of edge nodes and core nodes, the control ...This paper presents a novel framework for IP Differentiated Services (DiffServ) over optical burst switching (OBS), namely, DS-OBS. The network architecture, functional model of edge nodes and core nodes, the control packet format, a novel burst assembly scheme at ingress nodes and scheduling algorithm of core nodes are presented. The basic idea is to apply DiffServ capable burst assembly at ingress nodes and perform different per hop behavior (PHB) electronic treatments for control packets of different QoS class services at core nodes. Simulation results show that the proposed schemes can provide the best differentiated service for expedited forwarding (EF), assured forwarding (AF) and best effort (BE) services in terms of end-to-end delay, throughput and IP packet loss probability. Keywords IP quality of service - differentiated service - per hop behavior - optical burst switching NoteThis work is supported by the National Natural Science Foundation of China (Grant No.90304004), the National Hi-Tech Development 863 Program of China (Grant No.2003AA121540), and the research grants by the Ministry of Education of China (Grant No.204125), the Chongqing Education Commission (Grant No.050309) and the Chongqing Science Commission.展开更多
This paper proposes an effective method for reducing test data volume undermultiple scan chain designs. The proposed method is based on reduction of distinct scan vectorsusing selective don't-care identification. ...This paper proposes an effective method for reducing test data volume undermultiple scan chain designs. The proposed method is based on reduction of distinct scan vectorsusing selective don't-care identification. Selective don't-care identification is repeatedlyexecuted under condition that each bit of frequent scan vectors is fixed to binary values (0 or 1).Besides, a code extension technique is adopted for improving compression efficiency with keepingdecompressor circuits simple in the manner that the code length for infrequent scan vectors isdesigned as double of that for frequent ones. The effectiveness of the proposed method is shownthrough experiments for ISCAS'89 and ITC'99 benchmark circuits.展开更多
For a class of SISO nonlinear control systems with parameter uncertainty an almost disturbance decoupling problem with stability is defined and investigated. Back stepping technique provides a practical design method ...For a class of SISO nonlinear control systems with parameter uncertainty an almost disturbance decoupling problem with stability is defined and investigated. Back stepping technique provides a practical design method of controller, under which the $L<sub>2</sub>$ gain from the disturbance to the controlled output can be arbitrarily small subject to nonlinear uncertainties and the close-loop system is internally asymptotically stable.展开更多
At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST f...At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transit ion- graph of t he proposed B IS T scheme are analyzed. B ased on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.展开更多
Detection of path delay faults requires two-pattern tests. BIST technique provides a low-cost test solution. This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for...Detection of path delay faults requires two-pattern tests. BIST technique provides a low-cost test solution. This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for path delay testing. Given a set of pre-generated test-pairs with pre-determined fault coverage, a deterministic TPG is synthesized to apply the given test-pair set in a limited test time. To achieve this objective, configurable linear feedback shift register (LFSR) structures are used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is very efficient in terms of hardware size and speed performance. Simulation of academic benchmark circuits has given good results when compared to alternative solutions.展开更多
文摘This paper presents a new type of fault current limiter (FCL) based on fast closing switch, which is composed of a capacitor bank and a reactor in series. The main control component is a fast closing switch connected in parallel with the capacitors, which is driven by the electromagnetic repulsion force. It can response the order within 1 ms. When fault occurs, the switch closes and the capacitors are bypassed, and the fault current is limited by the reactor. Simulation analysis and experiment show that the electromagnetic repulsion force actuator can meet the demand of fast closing switch, it is feasible to develop the FCL with low cost and high reliability.
文摘This paper presents a novel framework for IP Differentiated Services (DiffServ) over optical burst switching (OBS), namely, DS-OBS. The network architecture, functional model of edge nodes and core nodes, the control packet format, a novel burst assembly scheme at ingress nodes and scheduling algorithm of core nodes are presented. The basic idea is to apply DiffServ capable burst assembly at ingress nodes and perform different per hop behavior (PHB) electronic treatments for control packets of different QoS class services at core nodes. Simulation results show that the proposed schemes can provide the best differentiated service for expedited forwarding (EF), assured forwarding (AF) and best effort (BE) services in terms of end-to-end delay, throughput and IP packet loss probability. Keywords IP quality of service - differentiated service - per hop behavior - optical burst switching NoteThis work is supported by the National Natural Science Foundation of China (Grant No.90304004), the National Hi-Tech Development 863 Program of China (Grant No.2003AA121540), and the research grants by the Ministry of Education of China (Grant No.204125), the Chongqing Education Commission (Grant No.050309) and the Chongqing Science Commission.
文摘This paper proposes an effective method for reducing test data volume undermultiple scan chain designs. The proposed method is based on reduction of distinct scan vectorsusing selective don't-care identification. Selective don't-care identification is repeatedlyexecuted under condition that each bit of frequent scan vectors is fixed to binary values (0 or 1).Besides, a code extension technique is adopted for improving compression efficiency with keepingdecompressor circuits simple in the manner that the code length for infrequent scan vectors isdesigned as double of that for frequent ones. The effectiveness of the proposed method is shownthrough experiments for ISCAS'89 and ITC'99 benchmark circuits.
基金This research is supportedby the Chinese Doctoral Foundation and the Natural Science Foundation of China.
文摘For a class of SISO nonlinear control systems with parameter uncertainty an almost disturbance decoupling problem with stability is defined and investigated. Back stepping technique provides a practical design method of controller, under which the $L<sub>2</sub>$ gain from the disturbance to the controlled output can be arbitrarily small subject to nonlinear uncertainties and the close-loop system is internally asymptotically stable.
基金the National Natural Science Foundation of China under grant Nos.69976002and 69733010.
文摘At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transit ion- graph of t he proposed B IS T scheme are analyzed. B ased on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.
基金This work was supported in part by the National Natural Science FOundation of China under grant No.69976002 and in part by the
文摘Detection of path delay faults requires two-pattern tests. BIST technique provides a low-cost test solution. This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for path delay testing. Given a set of pre-generated test-pairs with pre-determined fault coverage, a deterministic TPG is synthesized to apply the given test-pair set in a limited test time. To achieve this objective, configurable linear feedback shift register (LFSR) structures are used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is very efficient in terms of hardware size and speed performance. Simulation of academic benchmark circuits has given good results when compared to alternative solutions.
