An extension to texture mapping is given in this paper for improving theefficiency of image-based rendering. For a depth image with an orthogonal displacement at eachpixel, it is decomposed by the displacement into a ...An extension to texture mapping is given in this paper for improving theefficiency of image-based rendering. For a depth image with an orthogonal displacement at eachpixel, it is decomposed by the displacement into a series of layered textures (LTs) with each onehaving the same displacement for all its texels. Meanwhile, some texels of the layered textures areinterpolated for obtaining a continuous 3D approximation of the model represented in the depthimage. Thus, the plane-to-plane texture mapping can be used to map these layered textures to producenovel views and the advantages can be obtained as follows: accelerating the rendering speed,supporting the 3D surface details and view motion parallax, and avoiding the expensive task ofhole-filling in the rendering stage. Experimental results show the new method can producehigh-quality images and run faster than many famous image-based rendering techniques.展开更多
This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it f...This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.展开更多
文摘An extension to texture mapping is given in this paper for improving theefficiency of image-based rendering. For a depth image with an orthogonal displacement at eachpixel, it is decomposed by the displacement into a series of layered textures (LTs) with each onehaving the same displacement for all its texels. Meanwhile, some texels of the layered textures areinterpolated for obtaining a continuous 3D approximation of the model represented in the depthimage. Thus, the plane-to-plane texture mapping can be used to map these layered textures to producenovel views and the advantages can be obtained as follows: accelerating the rendering speed,supporting the 3D surface details and view motion parallax, and avoiding the expensive task ofhole-filling in the rendering stage. Experimental results show the new method can producehigh-quality images and run faster than many famous image-based rendering techniques.
文摘This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.
