This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis...This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis method for power grid optimization, the proposed simulator introduces hardware-oriented fixed point arithmetic instead of floating point arithmetic. It accomplishes the high accuracy by selecting appropriate time step of the simulation;2) The simulator achieves high speed simulation by developing dedicated hardware and adopting parallel processing. Experiments prove that the proposed simulator using 80 MHz FPGA and eight parallel processing achieves 35 times faster simulation than software processing with 2.8 GHz CPU while maintaining almost same accuracy in comparison with SPICE simulation.展开更多
With the recent advances of the VLSI technologies, stabilizing the physical behavior of VLSI chips is becoming a very complicated problem. Power grid optimization is required to minimize the risks of timing error by I...With the recent advances of the VLSI technologies, stabilizing the physical behavior of VLSI chips is becoming a very complicated problem. Power grid optimization is required to minimize the risks of timing error by IR drop, defects by electro migration (EM), and manufacturing cost by the chip size. This problem includes complicated tradeoff relationships. We propose a new approach by observing the direct objectives of manufacturing cost, and timing error risk caused by IR drop and EM. The manufacturing cost is based on yield for LSI chip. The optimization is executed in early phase of the physical design, and the purpose is to find the rough budget of decoupling capacitors that may cause block size increase. Rough budgeting of the power wire width is also determined simultaneously. The experimental result shows that our approach enables selection of a cost sensitive result or a performance sensitive result in early physical design phase.展开更多
文摘This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis method for power grid optimization, the proposed simulator introduces hardware-oriented fixed point arithmetic instead of floating point arithmetic. It accomplishes the high accuracy by selecting appropriate time step of the simulation;2) The simulator achieves high speed simulation by developing dedicated hardware and adopting parallel processing. Experiments prove that the proposed simulator using 80 MHz FPGA and eight parallel processing achieves 35 times faster simulation than software processing with 2.8 GHz CPU while maintaining almost same accuracy in comparison with SPICE simulation.
文摘With the recent advances of the VLSI technologies, stabilizing the physical behavior of VLSI chips is becoming a very complicated problem. Power grid optimization is required to minimize the risks of timing error by IR drop, defects by electro migration (EM), and manufacturing cost by the chip size. This problem includes complicated tradeoff relationships. We propose a new approach by observing the direct objectives of manufacturing cost, and timing error risk caused by IR drop and EM. The manufacturing cost is based on yield for LSI chip. The optimization is executed in early phase of the physical design, and the purpose is to find the rough budget of decoupling capacitors that may cause block size increase. Rough budgeting of the power wire width is also determined simultaneously. The experimental result shows that our approach enables selection of a cost sensitive result or a performance sensitive result in early physical design phase.
