This paper presents a preprocessing technique that can provide the improved quality of image robust to illumination changes. First, in order to enhance the image contrast, we proposed new adaptive histogram transforma...This paper presents a preprocessing technique that can provide the improved quality of image robust to illumination changes. First, in order to enhance the image contrast, we proposed new adaptive histogram transformation combining histogram equalization and histogram specification. Here, by examining the characteristic of histogram distribution shape, we determine the appropriate target distribution. Next, applying the histogram equalization with an image histogram, we have obtained the uniform distribution of pixel values, and then we have again carried out the histogram transformation using an inverse of target distribution function. Finally we have conducted various experiments that can enhance the quality of image by applying our method with various standard images. The experimental results show that the proposed method can achieve moderately good image enhancement results.展开更多
In this paper, the iterative Vertical-Bell-lab Layered Space-Time (V-BLAST) decoding algorithm of an Adaptive Modulation and Coding (AMC) system is proposed, and the corresponding MIMO scheme is analyzed. The proposed...In this paper, the iterative Vertical-Bell-lab Layered Space-Time (V-BLAST) decoding algorithm of an Adaptive Modulation and Coding (AMC) system is proposed, and the corresponding MIMO scheme is analyzed. The proposed decoding algorithm adopts iteratively extrinsic information from a Maximum A Posteriori (MAP) decoder as an a priori probability in the two decoding procedures of the V-BLAST scheme of ordering and slicing in an AMC system. Furthermore, the performance of the proposed decoding algorithm is compared with that of a conventional V-BLAST decoding algorithm and a Maximum Likelihood (ML) decoding algorithm in the combined system of an AMC scheme and a V-BLAST scheme. In this analysis, each MIMO schemes are assumed to be parts of the system for performance improvement.展开更多
The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ couplin...The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.展开更多
This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology pa...This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.展开更多
文摘This paper presents a preprocessing technique that can provide the improved quality of image robust to illumination changes. First, in order to enhance the image contrast, we proposed new adaptive histogram transformation combining histogram equalization and histogram specification. Here, by examining the characteristic of histogram distribution shape, we determine the appropriate target distribution. Next, applying the histogram equalization with an image histogram, we have obtained the uniform distribution of pixel values, and then we have again carried out the histogram transformation using an inverse of target distribution function. Finally we have conducted various experiments that can enhance the quality of image by applying our method with various standard images. The experimental results show that the proposed method can achieve moderately good image enhancement results.
文摘In this paper, the iterative Vertical-Bell-lab Layered Space-Time (V-BLAST) decoding algorithm of an Adaptive Modulation and Coding (AMC) system is proposed, and the corresponding MIMO scheme is analyzed. The proposed decoding algorithm adopts iteratively extrinsic information from a Maximum A Posteriori (MAP) decoder as an a priori probability in the two decoding procedures of the V-BLAST scheme of ordering and slicing in an AMC system. Furthermore, the performance of the proposed decoding algorithm is compared with that of a conventional V-BLAST decoding algorithm and a Maximum Likelihood (ML) decoding algorithm in the combined system of an AMC scheme and a V-BLAST scheme. In this analysis, each MIMO schemes are assumed to be parts of the system for performance improvement.
文摘The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.
基金supported by the Project SMDP-II,MCIT,Govt.of India
文摘This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.
