Data security plays a vital role in the current scenario due to the advanced and sophisticated data access techniques. Present development in data access is always a threat to data that are stored in electronic device...Data security plays a vital role in the current scenario due to the advanced and sophisticated data access techniques. Present development in data access is always a threat to data that are stored in electronic devices. Among all the forms of data, image is an important aspect that still needs methodologies to be stored securely. This work focuses on a novel technique to secure images using inter block difference and advanced encryption standard (AES). The AES algorithm is chosen for encryption since there is no prevalent attack that is successful in analyzing it. Instead of encrypting the entire image, only a part of the image is encrypted. The proposed work is found to reduce the encryption overhead in a significant way and at the same time preserves the safety of the image. It is also observed that the decryption is done in an efficient and time preserving manner.展开更多
Advanced technology used for arithmetic computing application,comprises greater number of approximatemultipliers and approximate adders.Truncation and Rounding-based Scalable ApproximateMultiplier(TRSAM)distinguish a ...Advanced technology used for arithmetic computing application,comprises greater number of approximatemultipliers and approximate adders.Truncation and Rounding-based Scalable ApproximateMultiplier(TRSAM)distinguish a variety of modes based on height(h)and truncation(t)as TRSAM(h,t)in the architecture.This TRSAM operation produces higher absolute error in Least Significant Bit(LSB)data shift unit.A new scalable approximate multiplier approach that uses truncation and rounding TRSAM(3,7)is proposed to increase themultiplier accuracy.With the help of foremost one bit architecture,the proposed scalable approximate multiplier approach reduces the partial products.The proposed approximate TRSAM multiplier architecture gives better results in terms of area,delay,and power.The accuracy of 95.2%and the energy utilization of 24.6 nJ is observed in the proposed multiplier design.The proposed approach shows 0.11%,0.23%,and 0.24%less Mean Absolute Relative Error(MARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.It also shows 0.13%,0.19%,and 0.2%less Variance of Absolute Relative Error(VARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.The proposed approach is implemented with Field-Programmable Gate Array(FPGA)and shows the delay of 3.640,6.481,12.505,22.572,and 36.893 ns for the input of 8-bit,16-bit,32-bit,64-bit,and 128-bit respectively.The proposed approach is applied in digital filters designwhich shows the Peak-Signal-to-NoiseRatio(PSNR)of 25.05 dB and Structural Similarity Index Measure(SSIM)of 0.98 with 393 pJ energy consumptions when used in image application.The proposed approach is simulated with Xilinx and MATLAB and implemented with FPGA.展开更多
A Rectangular Microstrip Patch Antenna model is proposed using air as a substrate to study the characteristics of designed antenna. The dimensions of designed antenna are 17 mm × 16.66 mm with substrate at freque...A Rectangular Microstrip Patch Antenna model is proposed using air as a substrate to study the characteristics of designed antenna. The dimensions of designed antenna are 17 mm × 16.66 mm with substrate at frequency 3.525 GHz. In this paper, the simulation is performed by using software Computer Simulation Technology (CST) Microwave studio based on finite difference time domain technique. The characterization of the designed antenna was analyzed in terms of return loss, bandwidth, directivity, gain, radiation pattern, VSWR.展开更多
We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （perfor...We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.展开更多
文摘Data security plays a vital role in the current scenario due to the advanced and sophisticated data access techniques. Present development in data access is always a threat to data that are stored in electronic devices. Among all the forms of data, image is an important aspect that still needs methodologies to be stored securely. This work focuses on a novel technique to secure images using inter block difference and advanced encryption standard (AES). The AES algorithm is chosen for encryption since there is no prevalent attack that is successful in analyzing it. Instead of encrypting the entire image, only a part of the image is encrypted. The proposed work is found to reduce the encryption overhead in a significant way and at the same time preserves the safety of the image. It is also observed that the decryption is done in an efficient and time preserving manner.
文摘Advanced technology used for arithmetic computing application,comprises greater number of approximatemultipliers and approximate adders.Truncation and Rounding-based Scalable ApproximateMultiplier(TRSAM)distinguish a variety of modes based on height(h)and truncation(t)as TRSAM(h,t)in the architecture.This TRSAM operation produces higher absolute error in Least Significant Bit(LSB)data shift unit.A new scalable approximate multiplier approach that uses truncation and rounding TRSAM(3,7)is proposed to increase themultiplier accuracy.With the help of foremost one bit architecture,the proposed scalable approximate multiplier approach reduces the partial products.The proposed approximate TRSAM multiplier architecture gives better results in terms of area,delay,and power.The accuracy of 95.2%and the energy utilization of 24.6 nJ is observed in the proposed multiplier design.The proposed approach shows 0.11%,0.23%,and 0.24%less Mean Absolute Relative Error(MARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.It also shows 0.13%,0.19%,and 0.2%less Variance of Absolute Relative Error(VARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.The proposed approach is implemented with Field-Programmable Gate Array(FPGA)and shows the delay of 3.640,6.481,12.505,22.572,and 36.893 ns for the input of 8-bit,16-bit,32-bit,64-bit,and 128-bit respectively.The proposed approach is applied in digital filters designwhich shows the Peak-Signal-to-NoiseRatio(PSNR)of 25.05 dB and Structural Similarity Index Measure(SSIM)of 0.98 with 393 pJ energy consumptions when used in image application.The proposed approach is simulated with Xilinx and MATLAB and implemented with FPGA.
文摘A Rectangular Microstrip Patch Antenna model is proposed using air as a substrate to study the characteristics of designed antenna. The dimensions of designed antenna are 17 mm × 16.66 mm with substrate at frequency 3.525 GHz. In this paper, the simulation is performed by using software Computer Simulation Technology (CST) Microwave studio based on finite difference time domain technique. The characterization of the designed antenna was analyzed in terms of return loss, bandwidth, directivity, gain, radiation pattern, VSWR.
文摘We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.
