Taking into account the fact that the computer systems, as the implementations of Turing machine, are physical devices, the paper shows considerations in which hard drive behavior will be presented in terms of statist...Taking into account the fact that the computer systems, as the implementations of Turing machine, are physical devices, the paper shows considerations in which hard drive behavior will be presented in terms of statistical mechanics. Because computer is a machine, its analysis cannot be based only on mathematical models apart of physical conditions. In the paper it will be presented a very narrow part this problem – an analysis of hard drive behavior in the context of the power-law distributions. We will focus only on four selected hard drive parameters, i.e. the rate of transfer bytes to or from the disk during the read or write, the number of pending requests to the disk and the rate of read operations. Our research was performed under the Windows operating system and this allows to make a statistical analysis for the possible occurrence of power-laws representing the lack of characteristic scale for considered processes. This property will be confirmed in all analyzed cases. A presented study can help describing the behavior of the whole computer system in terms of physics of computer processing.展开更多
New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., FPGAs）. One of the new promising architect...New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., FPGAs）. One of the new promising architectures axe Configurable System-on-Chip （CSoC） solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller （mTC） unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results axe given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.展开更多
文摘Taking into account the fact that the computer systems, as the implementations of Turing machine, are physical devices, the paper shows considerations in which hard drive behavior will be presented in terms of statistical mechanics. Because computer is a machine, its analysis cannot be based only on mathematical models apart of physical conditions. In the paper it will be presented a very narrow part this problem – an analysis of hard drive behavior in the context of the power-law distributions. We will focus only on four selected hard drive parameters, i.e. the rate of transfer bytes to or from the disk during the read or write, the number of pending requests to the disk and the rate of read operations. Our research was performed under the Windows operating system and this allows to make a statistical analysis for the possible occurrence of power-laws representing the lack of characteristic scale for considered processes. This property will be confirmed in all analyzed cases. A presented study can help describing the behavior of the whole computer system in terms of physics of computer processing.
文摘New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., FPGAs）. One of the new promising architectures axe Configurable System-on-Chip （CSoC） solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller （mTC） unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results axe given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.
