Novel fault-tolerant architectures for bit-parallel polynomial basis multiplier over GF（2^m）, which can correct the erroneous outputs using linear code, are presented. A parity prediction circuit based on the code g...Novel fault-tolerant architectures for bit-parallel polynomial basis multiplier over GF（2^m）, which can correct the erroneous outputs using linear code, are presented. A parity prediction circuit based on the code generator polynomial that leads lower space overhead has been designed. For bit-parallel architectures, the Moreover, there is incorporation of space overhead only marginal time error-correction is about 11%. overhead due to capability that amounts to 3.5% in case of the bit-parallel multiplier. Unlike the existing concurrent error correction （CEC） multipliers or triple modular redundancy （TMR） techniques for single error correction, the proposed architectures have multiple error-correcting capabilities.展开更多
We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gat...We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gates instead of AND and XOR gates. We show that our multiplier for type-1 and type-2 normal bases saves about 8% and 16%, respectively, in space complexity as compared to existing normal basis multipliers. Finally, the proposed architecture has regular and modular con-figurations and is well suited to VLSI implementations.展开更多
Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algor...Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algorithm over GF（2^m） using the dual basis representation. Based on the proposed algorithm, a parallel-in parallel-out systolic multiplier is presented, The architecture is optimized in order to minimize the silicon covered area （transistor count）. The experimental results reveal that the proposed bit-parallel multiplier saves about 65% space complexity and 33% time complexity as compared to the traditional multipliers for a general polynomial and dual basis of GF（2^m）.展开更多
In general, there are three popular basis representations, standard （canonical, polynomial） basis, normal basis, and dual basis, for representing elements in GF（2^m）. Various basis representations have their disti...In general, there are three popular basis representations, standard （canonical, polynomial） basis, normal basis, and dual basis, for representing elements in GF（2^m）. Various basis representations have their distinct advantages and have their different associated multiplication architectures. In this paper, we will present a unified systolic multiplication architecture, by employing Hankel matrix-vector multiplication, for various basis representations. For various element representation in GF（2^m）, we will show that various basis multiplications can be performed by Hankel matrix-vector multiplications. A comparison with existing and similar structures has shown that time complexities. the proposed architectures perform well both in space and展开更多
基金supported by the National Science Council of the Republic of China,Taiwan,under Grant No.NSC 98-2221-E-262-007
文摘Novel fault-tolerant architectures for bit-parallel polynomial basis multiplier over GF（2^m）, which can correct the erroneous outputs using linear code, are presented. A parity prediction circuit based on the code generator polynomial that leads lower space overhead has been designed. For bit-parallel architectures, the Moreover, there is incorporation of space overhead only marginal time error-correction is about 11%. overhead due to capability that amounts to 3.5% in case of the bit-parallel multiplier. Unlike the existing concurrent error correction （CEC） multipliers or triple modular redundancy （TMR） techniques for single error correction, the proposed architectures have multiple error-correcting capabilities.
文摘We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gates instead of AND and XOR gates. We show that our multiplier for type-1 and type-2 normal bases saves about 8% and 16%, respectively, in space complexity as compared to existing normal basis multipliers. Finally, the proposed architecture has regular and modular con-figurations and is well suited to VLSI implementations.
文摘Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algorithm over GF（2^m） using the dual basis representation. Based on the proposed algorithm, a parallel-in parallel-out systolic multiplier is presented, The architecture is optimized in order to minimize the silicon covered area （transistor count）. The experimental results reveal that the proposed bit-parallel multiplier saves about 65% space complexity and 33% time complexity as compared to the traditional multipliers for a general polynomial and dual basis of GF（2^m）.
文摘In general, there are three popular basis representations, standard （canonical, polynomial） basis, normal basis, and dual basis, for representing elements in GF（2^m）. Various basis representations have their distinct advantages and have their different associated multiplication architectures. In this paper, we will present a unified systolic multiplication architecture, by employing Hankel matrix-vector multiplication, for various basis representations. For various element representation in GF（2^m）, we will show that various basis multiplications can be performed by Hankel matrix-vector multiplications. A comparison with existing and similar structures has shown that time complexities. the proposed architectures perform well both in space and
