Polar codes have become increasingly popular recently because of their capacity achieving property.In this paper,a memory efficient stage-combined belief propagation(BP) decoder design for polar codes is presented.Fir...Polar codes have become increasingly popular recently because of their capacity achieving property.In this paper,a memory efficient stage-combined belief propagation(BP) decoder design for polar codes is presented.Firstly,we briefly reviewed the conventional BP decoding algorithm.Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced.Based on this stage-combined decoding algorithm,a memory-efficient polar BP decoder is designed.The demonstrated decoder design achieves 50%memory and decoding latency reduction in the cost of some combinational logic complexity overhead.The proposed decoder is synthesized under TSMC 45 nm Low Power CMOS technology.It achieves 0.96 Gb/s throughput with 14.2mm^2 area when code length N=2^(16)which reduces 51.5%decoder area compared with the conventional decoder design.展开更多
A 30 MHz voltage-mode controlled buck converter with fast transient responses is presented.An improved differential difference amplifier(DDA)-based Type-III compensator is proposed to reduce the settling times of the ...A 30 MHz voltage-mode controlled buck converter with fast transient responses is presented.An improved differential difference amplifier(DDA)-based Type-III compensator is proposed to reduce the settling times of the converter during load transients,and to achieve near-optimal transient responses with simple PWM control only.Moreover,a hybrid scheme using a digital linear regulator with automatic transient detection and seamless loop transition is proposed to further improve the transient responses.By monitoring the output voltage of the compensator instead of the output voltage of the converter,the proposed hybrid scheme can reduce undershoot and overshoot effectively with good noise immunity and without interrupting the PWM loop.The converter was fabricated in a 0.13μm standard CMOS process using 3.3 V devices.With an input voltage of 3.3 V,the measured peak efficiencies at the output voltages of 2.4,1.8,and 1.2 V are 90.7%,88%,and 83.6%,respectively.With a load step of 1.25 A and rise and fall times of 2 ns,the measured 1%settling times were 220 and 230 ns,with undershoot and overshoot with PWM control of 72 and 76 mV,respectively.They were further reduced to 36 and 38 mV by using the proposed hybrid scheme,and 1%settling times were also reduced to 125 ns.展开更多
For communication systems with heavy burst noise, an optimal Forward Error Correction(FEC) scheme is expected to have a large burst error correction capability while simultaneously owning moderate random error correct...For communication systems with heavy burst noise, an optimal Forward Error Correction(FEC) scheme is expected to have a large burst error correction capability while simultaneously owning moderate random error correction capability. This letter presents a new FEC scheme based on multiple-symbol interleaved Reed-Solomon codes and an associated two-pass decoding algorithm. It is shown that the proposed multi-symbol interleaved Reed-Solomon scheme can achieve nearly twice as much as the burst error correction capability of conventional single-symbol interleaved Reed-Solomon codes with the same code length and code rate.展开更多
基金jointly supported by the National Nature Science Foundation of China under Grant No.61370040 and 61006018the Fundamental Research Funds for the Central Universities+1 种基金the Priority Academic Program Development of Jiangsu Higher Education InstitutionsOpen Project of State Key Laboratory of ASIC & System(Fudan University)12KF006
文摘Polar codes have become increasingly popular recently because of their capacity achieving property.In this paper,a memory efficient stage-combined belief propagation(BP) decoder design for polar codes is presented.Firstly,we briefly reviewed the conventional BP decoding algorithm.Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced.Based on this stage-combined decoding algorithm,a memory-efficient polar BP decoder is designed.The demonstrated decoder design achieves 50%memory and decoding latency reduction in the cost of some combinational logic complexity overhead.The proposed decoder is synthesized under TSMC 45 nm Low Power CMOS technology.It achieves 0.96 Gb/s throughput with 14.2mm^2 area when code length N=2^(16)which reduces 51.5%decoder area compared with the conventional decoder design.
文摘A 30 MHz voltage-mode controlled buck converter with fast transient responses is presented.An improved differential difference amplifier(DDA)-based Type-III compensator is proposed to reduce the settling times of the converter during load transients,and to achieve near-optimal transient responses with simple PWM control only.Moreover,a hybrid scheme using a digital linear regulator with automatic transient detection and seamless loop transition is proposed to further improve the transient responses.By monitoring the output voltage of the compensator instead of the output voltage of the converter,the proposed hybrid scheme can reduce undershoot and overshoot effectively with good noise immunity and without interrupting the PWM loop.The converter was fabricated in a 0.13μm standard CMOS process using 3.3 V devices.With an input voltage of 3.3 V,the measured peak efficiencies at the output voltages of 2.4,1.8,and 1.2 V are 90.7%,88%,and 83.6%,respectively.With a load step of 1.25 A and rise and fall times of 2 ns,the measured 1%settling times were 220 and 230 ns,with undershoot and overshoot with PWM control of 72 and 76 mV,respectively.They were further reduced to 36 and 38 mV by using the proposed hybrid scheme,and 1%settling times were also reduced to 125 ns.
文摘For communication systems with heavy burst noise, an optimal Forward Error Correction(FEC) scheme is expected to have a large burst error correction capability while simultaneously owning moderate random error correction capability. This letter presents a new FEC scheme based on multiple-symbol interleaved Reed-Solomon codes and an associated two-pass decoding algorithm. It is shown that the proposed multi-symbol interleaved Reed-Solomon scheme can achieve nearly twice as much as the burst error correction capability of conventional single-symbol interleaved Reed-Solomon codes with the same code length and code rate.
