High performance analog and mixed signal circuits are strongly demanded in todays’system on chip systems.They found pervasive applications in A/D or D/A conversion,power management,radio frequency(RF)signal sensing a...High performance analog and mixed signal circuits are strongly demanded in todays’system on chip systems.They found pervasive applications in A/D or D/A conversion,power management,radio frequency(RF)signal sensing and processing,clock generation,etc.In this special issue,we collected 7 comprehensive reviews and 2 research articles from leading research groups,which presented state-of-art design techniques and insight forecast of development trend in this hot area.展开更多
A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3...A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.展开更多
A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology t...A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.展开更多
This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input dat...This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.展开更多
Qinghaosu 1 isolated from Artemisia annua L. has attracted great interest in recent years owing to its unique chemical structure and potent antimalarial activity, especially against chloroquine-resistant faleiprum mal...Qinghaosu 1 isolated from Artemisia annua L. has attracted great interest in recent years owing to its unique chemical structure and potent antimalarial activity, especially against chloroquine-resistant faleiprum malaria. A series of studies have been carried out on its reactions, total synthesis and analogs.For preparation of more Qing-展开更多
文摘High performance analog and mixed signal circuits are strongly demanded in todays’system on chip systems.They found pervasive applications in A/D or D/A conversion,power management,radio frequency(RF)signal sensing and processing,clock generation,etc.In this special issue,we collected 7 comprehensive reviews and 2 research articles from leading research groups,which presented state-of-art design techniques and insight forecast of development trend in this hot area.
基金Project supported by the National Natural Science Foundation of China(Nos.60906009,60773025)the Postdoctoral Science Foundation of China(No.20090451423)the National Labs of Analog Integrated Circuits Foundation(No.9140C0901110902)
文摘A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.
文摘A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.
文摘This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.
文摘Qinghaosu 1 isolated from Artemisia annua L. has attracted great interest in recent years owing to its unique chemical structure and potent antimalarial activity, especially against chloroquine-resistant faleiprum malaria. A series of studies have been carried out on its reactions, total synthesis and analogs.For preparation of more Qing-
