High performance analog and mixed signal circuits are strongly demanded in todays’system on chip systems.They found pervasive applications in A/D or D/A conversion,power management,radio frequency(RF)signal sensing a...High performance analog and mixed signal circuits are strongly demanded in todays’system on chip systems.They found pervasive applications in A/D or D/A conversion,power management,radio frequency(RF)signal sensing and processing,clock generation,etc.In this special issue,we collected 7 comprehensive reviews and 2 research articles from leading research groups,which presented state-of-art design techniques and insight forecast of development trend in this hot area.展开更多
A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3...A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.展开更多
Rapid diagnosis of Salmonella is crucial for the effective control of food safety incidents, especially in regions with poor hygiene conditions. Polymerase chain reaction(PCR), as a promising tool for Salmonella detec...Rapid diagnosis of Salmonella is crucial for the effective control of food safety incidents, especially in regions with poor hygiene conditions. Polymerase chain reaction(PCR), as a promising tool for Salmonella detection, is facing a lack of simple and fast sensing methods that are compatible with field applications in resource-limited areas. In this work, we developed a sensing approach to identify PCR-amplified Salmonella genomic DNA with the naked eye in a snapshot. Based on the ratiometric fiuorescence signals from SYBR Green Ⅰ and Hydroxyl naphthol blue, positive samples stood out from negative ones with a distinct color pattern under UV exposure. The proposed sensing scheme enabled highly specific identification of Salmonella with a detection limit at the single-copy level. Also, as a supplement to the intuitive naked-eye visualization results, numerical analysis of the colored images was available with a smartphone app to extract RGB values from colored images. This work provides a simple, rapid, and user-friendly solution for PCR identification, which promises great potential in molecular diagnosis of Salmonella and other pathogens in field.展开更多
A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology t...A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.展开更多
This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input dat...This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.展开更多
文摘High performance analog and mixed signal circuits are strongly demanded in todays’system on chip systems.They found pervasive applications in A/D or D/A conversion,power management,radio frequency(RF)signal sensing and processing,clock generation,etc.In this special issue,we collected 7 comprehensive reviews and 2 research articles from leading research groups,which presented state-of-art design techniques and insight forecast of development trend in this hot area.
基金Project supported by the National Natural Science Foundation of China(Nos.60906009,60773025)the Postdoctoral Science Foundation of China(No.20090451423)the National Labs of Analog Integrated Circuits Foundation(No.9140C0901110902)
文摘A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.
基金supported by the Macao Science and Technology Development Fund(FDCT)(Nos.FDCT 0029/2021/A1,FDCT0002/2021/AKP,004/2023/SKL,0036/2021/APD)University of Macao(No.MYRG-GRG2023-00034-IME,SRG2024-00057IME)+2 种基金Dr.Stanley Ho Medical Development Foundation(No.SHMDF-OIRFS/2024/001)Zhuhai Huafa Group(No.HF-006-2021)Guangdong Science and Technology Department(No.2022A0505030022)。
文摘Rapid diagnosis of Salmonella is crucial for the effective control of food safety incidents, especially in regions with poor hygiene conditions. Polymerase chain reaction(PCR), as a promising tool for Salmonella detection, is facing a lack of simple and fast sensing methods that are compatible with field applications in resource-limited areas. In this work, we developed a sensing approach to identify PCR-amplified Salmonella genomic DNA with the naked eye in a snapshot. Based on the ratiometric fiuorescence signals from SYBR Green Ⅰ and Hydroxyl naphthol blue, positive samples stood out from negative ones with a distinct color pattern under UV exposure. The proposed sensing scheme enabled highly specific identification of Salmonella with a detection limit at the single-copy level. Also, as a supplement to the intuitive naked-eye visualization results, numerical analysis of the colored images was available with a smartphone app to extract RGB values from colored images. This work provides a simple, rapid, and user-friendly solution for PCR identification, which promises great potential in molecular diagnosis of Salmonella and other pathogens in field.
文摘A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.
文摘This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.
