The aim of this work is to model and analyze the behavior of a new smart nano force sensor.To do so,the carbon nanotube has been used as a suspended gate of a metal-oxide-semiconductor field-effect transistor(MOSFET)....The aim of this work is to model and analyze the behavior of a new smart nano force sensor.To do so,the carbon nanotube has been used as a suspended gate of a metal-oxide-semiconductor field-effect transistor(MOSFET).The variation of the applied force on the carbon nanotube(CNT)generates a variation of the capacity of the transistor oxide-gate and therefore the variation of the threshold voltage,which allows the MOSFET to become a capacitive nano force sensor.The sensitivity of the nano force sensor can reach 0.12431V/nN.This sensitivity is greater than results in the literature.We have found through this study that the response of the sensor depends strongly on the geometric and physical parameters of the CNT.From the results obtained in this study,it can be seen that the increase in the applied force increases the value of the MOSFET threshold voltage VTh.In this paper,we first used artificial neural networks to faithfully reproduce the response of the nano force sensor model.This neural model is called direct model.Then,secondly,we designed an inverse model called an intelligent sensor which allows linearization of the response of our developed force sensor.展开更多
The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specifi...The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters （ADCs）. All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters （white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages）. Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.展开更多
This paper presents a compact analytical model for the organic field-effect transistors （OFETs）, which describes two main aspects, the first one is related to the behavior in above threshold regime, while the other ...This paper presents a compact analytical model for the organic field-effect transistors （OFETs）, which describes two main aspects, the first one is related to the behavior in above threshold regime, while the other corresponds to the below threshold regime. The total drain current in the OFET device is calculated as the sum of two components, with the inclusion of a smooth transition function in order to take into account both regions using a single expression. A genetic algorithm based approach （GA） is investigated as a parameter extraction tool in the case of the compact OFET model to find the parameters＇ values from experimental data such as： mobility enhancement factor % threshold voltage VTh, subthreshold swing S, channel length modulation A, and knee region sharpness m. The comparison of the developed current model with the experimental data shows a good agreement in terms of the transfer and the output characteristics. Therefore, the GA based approach can be considered as a competitive candidate compared to the direct method.展开更多
We present a systematic study to create ultra-shallow junctions in n-type silicon substrates and investigate both pre-and post-annealing processes to create a processing strategy for potential applications in nano-dev...We present a systematic study to create ultra-shallow junctions in n-type silicon substrates and investigate both pre-and post-annealing processes to create a processing strategy for potential applications in nano-devices.Starting wafers were co-implanted with indium and C atoms at energies of 70 keV and 10 keV,respectively.A carefully chosen implantation schedule provides an abrupt ultra-shallow junction between 17 and 43 nm with suppressed sheet resistance and appropriate retained sheet carrier concentration at low thermal budget.A defect doping matrix,primarily the behavior and movement of co-implant generated interstitials at different annealing temperatures,may be engineered to form sufficiently activated ultra-shallow devices.展开更多
Development of graphene field effect transistors （GFETs） faces a serious challenge of graphene interface to the dielectric material. A single layer of intrinsic graphene has an average sheet resistance of the order ...Development of graphene field effect transistors （GFETs） faces a serious challenge of graphene interface to the dielectric material. A single layer of intrinsic graphene has an average sheet resistance of the order of 1-5 kΩ/□. The intrinsic nature of graphene leads to higher contact resistance yielding into the outstanding properties of the material. We design a graphene matrix with minimized sheet resistance of 0.185 kΩ/□ with Ag contacts. The developed matrices on silicon substrates provide a variety of transistor design options for subsequent fabrication. The graphene layer is developed over 400 nm nickel in such a way as to analyze hypersensitive electrical properties of the interface for exfoliation. This work identifies potential of the design in the applicability of few-layer GFETs with less process steps with the help of analyzing the effect of metal contact and post-process anneMing on its electrical fabrication.展开更多
This study focuses on a virtual synchronous machine(VSM) based on voltage source converters to mimic the behavior of synchronous machines(SMs) and improve the damping ratio of the power system. The VSM model is simpli...This study focuses on a virtual synchronous machine(VSM) based on voltage source converters to mimic the behavior of synchronous machines(SMs) and improve the damping ratio of the power system. The VSM model is simplified according to some assumptions(neglecting the speed variation and the stator transients) to allow for the possibility of dealing with low-frequency oscillation in large-scale systems with many VSMs. Furthermore, a virtual power system stabilizer(VPSS) structure is proposed and tuned using a method based on a linearized power system dynamic model. The linear and nonlinear analyses examine the stability of two modified versions of a 16-machine power system in which, in the first case, partial classical machines are replaced by VSMs, and in the second case, all SMs are replaced by VSMs. The simulation results of the case studies validate the efficiency of the proposed control strategy.展开更多
文摘The aim of this work is to model and analyze the behavior of a new smart nano force sensor.To do so,the carbon nanotube has been used as a suspended gate of a metal-oxide-semiconductor field-effect transistor(MOSFET).The variation of the applied force on the carbon nanotube(CNT)generates a variation of the capacity of the transistor oxide-gate and therefore the variation of the threshold voltage,which allows the MOSFET to become a capacitive nano force sensor.The sensitivity of the nano force sensor can reach 0.12431V/nN.This sensitivity is greater than results in the literature.We have found through this study that the response of the sensor depends strongly on the geometric and physical parameters of the CNT.From the results obtained in this study,it can be seen that the increase in the applied force increases the value of the MOSFET threshold voltage VTh.In this paper,we first used artificial neural networks to faithfully reproduce the response of the nano force sensor model.This neural model is called direct model.Then,secondly,we designed an inverse model called an intelligent sensor which allows linearization of the response of our developed force sensor.
文摘The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters （ADCs）. All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters （white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages）. Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.
文摘This paper presents a compact analytical model for the organic field-effect transistors （OFETs）, which describes two main aspects, the first one is related to the behavior in above threshold regime, while the other corresponds to the below threshold regime. The total drain current in the OFET device is calculated as the sum of two components, with the inclusion of a smooth transition function in order to take into account both regions using a single expression. A genetic algorithm based approach （GA） is investigated as a parameter extraction tool in the case of the compact OFET model to find the parameters＇ values from experimental data such as： mobility enhancement factor % threshold voltage VTh, subthreshold swing S, channel length modulation A, and knee region sharpness m. The comparison of the developed current model with the experimental data shows a good agreement in terms of the transfer and the output characteristics. Therefore, the GA based approach can be considered as a competitive candidate compared to the direct method.
文摘We present a systematic study to create ultra-shallow junctions in n-type silicon substrates and investigate both pre-and post-annealing processes to create a processing strategy for potential applications in nano-devices.Starting wafers were co-implanted with indium and C atoms at energies of 70 keV and 10 keV,respectively.A carefully chosen implantation schedule provides an abrupt ultra-shallow junction between 17 and 43 nm with suppressed sheet resistance and appropriate retained sheet carrier concentration at low thermal budget.A defect doping matrix,primarily the behavior and movement of co-implant generated interstitials at different annealing temperatures,may be engineered to form sufficiently activated ultra-shallow devices.
文摘Development of graphene field effect transistors （GFETs） faces a serious challenge of graphene interface to the dielectric material. A single layer of intrinsic graphene has an average sheet resistance of the order of 1-5 kΩ/□. The intrinsic nature of graphene leads to higher contact resistance yielding into the outstanding properties of the material. We design a graphene matrix with minimized sheet resistance of 0.185 kΩ/□ with Ag contacts. The developed matrices on silicon substrates provide a variety of transistor design options for subsequent fabrication. The graphene layer is developed over 400 nm nickel in such a way as to analyze hypersensitive electrical properties of the interface for exfoliation. This work identifies potential of the design in the applicability of few-layer GFETs with less process steps with the help of analyzing the effect of metal contact and post-process anneMing on its electrical fabrication.
文摘This study focuses on a virtual synchronous machine(VSM) based on voltage source converters to mimic the behavior of synchronous machines(SMs) and improve the damping ratio of the power system. The VSM model is simplified according to some assumptions(neglecting the speed variation and the stator transients) to allow for the possibility of dealing with low-frequency oscillation in large-scale systems with many VSMs. Furthermore, a virtual power system stabilizer(VPSS) structure is proposed and tuned using a method based on a linearized power system dynamic model. The linear and nonlinear analyses examine the stability of two modified versions of a 16-machine power system in which, in the first case, partial classical machines are replaced by VSMs, and in the second case, all SMs are replaced by VSMs. The simulation results of the case studies validate the efficiency of the proposed control strategy.
