As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they ...As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.展开更多
The epitaxial growth of a high-quality silicon layer on double-layer porous silicon by ultra-high vacuum/chemical vapour deposition has been reported. The two-step anodization process results in a double-layer porous ...The epitaxial growth of a high-quality silicon layer on double-layer porous silicon by ultra-high vacuum/chemical vapour deposition has been reported. The two-step anodization process results in a double-layer porous silicon structure with a different porosity. This double-layer porous silicon structure and an extended low-temperature annealing in a vacuum system was found to be helpful in subsequent silicon epitaxial growth. X-ray diffraction,cross-sectional transmission electron microscopy and spreading resistance testing were used in this work to study the properties of epitaxial silicon layers grown on the double-layer porous silicon. The results show that the epitaxial silicon layer is of good crystallinity and the same orientation with the silicon substrate and the porous silicon layer.展开更多
Neuromorphic vision hardware,embedded with multiple functions,has recently emerged as a potent platform for machine vision.To realize memory in sensor functions,reconfigurable and non-volatile manipulation of photocar...Neuromorphic vision hardware,embedded with multiple functions,has recently emerged as a potent platform for machine vision.To realize memory in sensor functions,reconfigurable and non-volatile manipulation of photocarriers is highly desirable.However,previous technologies bear mechanism challenges,such as the ambiguous optoelectronic memory mechanism and high potential barrier,resulting in a limited response speed and a high operating voltage.Here,for the first time,we propose a critical band-to-band tunnelling(BTBT)based device that combines sensing,integration and memory functions.The nearly infinitesimal barrier facilitates the tunnelling process,resulting in a broadband application range(94o nm).Furthermore,the observation of dual negative differential resistance(NDR)points confirms that the critical BTBT of photocarriers contributes to the sub-microsecond photomemory speed.Since the photomemory speed,with no motion blur,is important for motion detection,the critical BTBT memory is expected to enable moving target tracking and recognition,underscoring its superiority in intelligentperception.展开更多
A generally improved recycling folded cascode（IRFC） is analyzed and implemented.Analysis and comparisons among the IRFC,the original recycling folded cascode（RFC） and the conventional folded cascode （FC） are mad...A generally improved recycling folded cascode（IRFC） is analyzed and implemented.Analysis and comparisons among the IRFC,the original recycling folded cascode（RFC） and the conventional folded cascode （FC） are made,and it is shown that with the flexible structure of IRFC,significant enhancement in transconductance, slew rate and noise can be achieved.Prototype amplifiers were fabricated in 0.13μm technology.Measurement shows that IRFC has 3×enhancement in gain-bandwidth and slew rate over conventional FC,and the enhancement is 1.5x when compared with the RFC.展开更多
A new expression is proposed to analyze the linearization effectiveness of derivative superposition （DS） with large and small signal inputs, and different optimization methods of DS are found for different input mag...A new expression is proposed to analyze the linearization effectiveness of derivative superposition （DS） with large and small signal inputs, and different optimization methods of DS are found for different input magni tudes. A power amplifier driver （PAD） with largesignal optimized DS was implemented in 0.13/,m technology within a reconfigurable RF transmitter. The PAD is compatible with the GSM band at 900 MHz and the WCDMA band at 1.95 GHz, and it has a gain range of 44 dB with a step of 2 dB. Measurement results show that the over all OIP3 of the transmitter is better than 19 dBm, and the output referred 1dB compression point is better than 7.5 dBm.展开更多
基金supported by National Natural Science Foundation of China with granted No.61404175
文摘As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.
基金Supported by the National Natural Science Foundation of China under Grant No.69876007。
文摘The epitaxial growth of a high-quality silicon layer on double-layer porous silicon by ultra-high vacuum/chemical vapour deposition has been reported. The two-step anodization process results in a double-layer porous silicon structure with a different porosity. This double-layer porous silicon structure and an extended low-temperature annealing in a vacuum system was found to be helpful in subsequent silicon epitaxial growth. X-ray diffraction,cross-sectional transmission electron microscopy and spreading resistance testing were used in this work to study the properties of epitaxial silicon layers grown on the double-layer porous silicon. The results show that the epitaxial silicon layer is of good crystallinity and the same orientation with the silicon substrate and the porous silicon layer.
基金supported by the National Key Research and Development Programme of China(Grant No.2023YFB3611400)National Natural Science Foundation of China(Grant Nos.62327812,62361136587,62422410,62205360 and 62304229)+2 种基金Shanghai Rising-Star Programme(Grant No.24QA2711000)CAS Project for Young Scientists in Basic Research(Grant No.YSBR-113)CAS Pioneer Hundred Talents Program.
文摘Neuromorphic vision hardware,embedded with multiple functions,has recently emerged as a potent platform for machine vision.To realize memory in sensor functions,reconfigurable and non-volatile manipulation of photocarriers is highly desirable.However,previous technologies bear mechanism challenges,such as the ambiguous optoelectronic memory mechanism and high potential barrier,resulting in a limited response speed and a high operating voltage.Here,for the first time,we propose a critical band-to-band tunnelling(BTBT)based device that combines sensing,integration and memory functions.The nearly infinitesimal barrier facilitates the tunnelling process,resulting in a broadband application range(94o nm).Furthermore,the observation of dual negative differential resistance(NDR)points confirms that the critical BTBT of photocarriers contributes to the sub-microsecond photomemory speed.Since the photomemory speed,with no motion blur,is important for motion detection,the critical BTBT memory is expected to enable moving target tracking and recognition,underscoring its superiority in intelligentperception.
基金supported by Important National Science and Technology Specific Projects of China(No.2009ZX01031-003-002)the National High Technology Research and Development Program of China(No.2009AA011605)the Important National Science & Technology Specific Projects of China(No.2010ZX03001-004)
文摘A generally improved recycling folded cascode（IRFC） is analyzed and implemented.Analysis and comparisons among the IRFC,the original recycling folded cascode（RFC） and the conventional folded cascode （FC） are made,and it is shown that with the flexible structure of IRFC,significant enhancement in transconductance, slew rate and noise can be achieved.Prototype amplifiers were fabricated in 0.13μm technology.Measurement shows that IRFC has 3×enhancement in gain-bandwidth and slew rate over conventional FC,and the enhancement is 1.5x when compared with the RFC.
基金Project supported by the Important National Science and Technology Specific Projects of China(Nos.2009ZX01031-003-002, 2010ZX03001-004)the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A new expression is proposed to analyze the linearization effectiveness of derivative superposition （DS） with large and small signal inputs, and different optimization methods of DS are found for different input magni tudes. A power amplifier driver （PAD） with largesignal optimized DS was implemented in 0.13/,m technology within a reconfigurable RF transmitter. The PAD is compatible with the GSM band at 900 MHz and the WCDMA band at 1.95 GHz, and it has a gain range of 44 dB with a step of 2 dB. Measurement results show that the over all OIP3 of the transmitter is better than 19 dBm, and the output referred 1dB compression point is better than 7.5 dBm.
