This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. ...This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. A high V_t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin（RSNM） due to the bit-line isolation during the read. Static noise margins for data read（RSNM）, write（WSNM）, read delay, write delay, data retention voltage（DRV）, leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8 T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.展开更多
文摘This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. A high V_t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin（RSNM） due to the bit-line isolation during the read. Static noise margins for data read（RSNM）, write（WSNM）, read delay, write delay, data retention voltage（DRV）, leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8 T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.
