To overcome disadvantages of traditional worst-case execution time （WCET） analysis approaches, we propose a new WCET analysis approach based on independent paths for ARM programs. Based on the results of program flo...To overcome disadvantages of traditional worst-case execution time （WCET） analysis approaches, we propose a new WCET analysis approach based on independent paths for ARM programs. Based on the results of program flow analysis, it reduces and partitions the control flow graph of the program and obtains a directed graph. Using linear combinations of independent paths of the directed graph, a set of feasible paths can be generated that gives complete coverage in terms of the program paths considered. Their timing measurements and execution counts of program segments are derived from a limited number of measurements of an instrumented version of the program. After the timing measurement of the feasible paths are linearly expressed by the execution times of program seg-ments, a system of equations is derived as a constraint problem, from which we can obtain the execution times of program segments. By assigning the execution times of program segments to weights of edges in the directed graph, the WCET estimate can be calculated on the basis of graph-theoretical techniques. Comparing our WCET estimate with the WCET measurement obtained by the exhaustive measurement, the maximum error ratio is only 8.259 3 %. It is shown that the proposed approach is an effective way to obtain the safe and tight WCET estimate for ARM programs.展开更多
As mobile edge computing continues to develop,the demand for resource-intensive applications is steadily increasing,placing a significant strain on edge nodes.These nodes are normally subject to various constraints,fo...As mobile edge computing continues to develop,the demand for resource-intensive applications is steadily increasing,placing a significant strain on edge nodes.These nodes are normally subject to various constraints,for instance,limited processing capability,a few energy sources,and erratic availability being some of the common ones.Correspondingly,these problems require an effective task allocation algorithmto optimize the resources through continued high system performance and dependability in dynamic environments.This paper proposes an improved Particle Swarm Optimization technique,known as IPSO,for multi-objective optimization in edge computing to overcome these issues.To this end,the IPSO algorithm tries to make a trade-off between two important objectives,which are energy consumption minimization and task execution time reduction.Because of global optimal position mutation and dynamic adjustment to inertia weight,the proposed optimization algorithm can effectively distribute tasks among edge nodes.As a result,it reduces the execution time of tasks and energy consumption.In comparative assessments carried out by IPSO with benchmark methods such as Energy-aware Double-fitness Particle Swarm Optimization(EADPSO)and ICBA,IPSO provides better results than these algorithms.For the maximum task size,when compared with the benchmark methods,IPSO reduces the execution time by 17.1%and energy consumption by 31.58%.These results allow the conclusion that IPSO is an efficient and scalable technique for task allocation at the edge environment.It provides peak efficiency while handling scarce resources and variable workloads.展开更多
As data volume grows, many enterprises are considering using MapReduce for its simplicity. However, how to evaluate the performance improvement before deployment is still an issue. Current researches of MapReduce perf...As data volume grows, many enterprises are considering using MapReduce for its simplicity. However, how to evaluate the performance improvement before deployment is still an issue. Current researches of MapReduce performance are mainly based on monitoring and simulation, and lack mathematical models. In this paper, we present a simple but powerful performance model for the prediction of the execution time of a MapReduce program with limited resources. We study each component of MapReduce framework, and analyze the relation between the overall performance and the number of mappers and reducers based on our model. Two typical MapReduce programs are evaluated in a small cluster with 13 nodes. Experimental results show that the mathematical performance model can estimate the execution time of MapReduce programs reliably. According to our model, number of mappers and reducers can be tuned to form a better execution pipeline and lead to better performance. The model also points out potential bottlenecks of the framework and future improvement.展开更多
Consensus of creativity research suggests that the measurement of both originality and valuableness is necessary when designing creativity tasks.However,few studies have emphasized valuableness when exploring underlyi...Consensus of creativity research suggests that the measurement of both originality and valuableness is necessary when designing creativity tasks.However,few studies have emphasized valuableness when exploring underlying neural substrates of creative thinking.The present study employs product-based creativity tasks that measure both originality and valuableness in an exploration of the dynamic relationship between the default mode(DMN),executive control(ECN),and salience(SN)networks through time windows.This methodology highlights relevance,or valuableness,in creativity evaluation as opposed to divergent thinking tasks solely measuring originality.The researchers identified seven brain regions belonging to the ECN,DMN,and SN as regions of interest(ROIs),as well as four representative seeds to analyze functional connectivity in 25 college student participants.Results showed that all of the identified ROIs were involved during the creative task.The insula,precuneus,and ventrolateral prefrontal cortex(vlPFC)remained active across all stages of product-based creative thinking.Moreover,the connectivity analyses revealed varied interaction patterns of DMN,ECN,and SN at different thinking stages.The integrated findings of the whole brain,ROI,and connectivity analyses suggest a trend that the DMN and SN(which relate to bottom-up thinking)attenuate as time proceeds,whereas the vlPFC(which relates to top-down thinking)gets stronger at later stages;these findings reflect the nature of our creativity tasks and decision-making of valuableness in later stages.Based on brain region activation throughout execution of the task,we propose that product-based creative process may include three stages:exploration and association,incubation and insight,and finally,evaluation and decision making.This model provides a thinking frame for further research and classroom instruction.展开更多
In many real-time resource-constrained embedded systems, highly-predictable system behavior is a key design requirement. The “time-triggered co-operative” (TTC) scheduling algorithm provides a good match for a wide ...In many real-time resource-constrained embedded systems, highly-predictable system behavior is a key design requirement. The “time-triggered co-operative” (TTC) scheduling algorithm provides a good match for a wide range of low-cost embedded applications. As a consequence of the resource, timing, and power constraints, the implementation of such algorithm is often far from trivial. Thus, basic implementation of TTC algorithm can result in excessive levels of task jitter which may jeopardize the predictability of many time-critical applications using this algorithm. This paper discusses the main sources of jitter in earlier TTC implementations and develops two alternative implementations – based on the employment of “sandwich delay” (SD) mechanisms – to reduce task jitter in TTC system significantly. In addition to jitter levels at task release times, we also assess the CPU, memory and power requirements involved in practical implementations of the proposed schedulers. The paper concludes that the TTC scheduler implementation using “multiple timer interrupt” (MTI) technique achieves better performance in terms of timing behavior and resource utilization as opposed to the other implementation which is based on a simple SD mechanism. Use of MTI technique is also found to provide a simple solution to “task overrun” problem which may degrade the performance of many TTC systems.展开更多
The paper presents the embedded real-time software-oriented requirements engineering environment—SREZ. It involves the whole process of software requirements engineering, including the definition, analysis and checki...The paper presents the embedded real-time software-oriented requirements engineering environment—SREZ. It involves the whole process of software requirements engineering, including the definition, analysis and checking of requirements ,specifications. We first explain the principles of the executable specification language RTRSM. Subsequently, we introduce the main functions of SREE, illustrate the methods and techniques of checking requirements specifications, especially how to perform simulation execution, combining prototyping method with RTRSM and animated representations. At last, we compare the SREE with other requirements specifications methods and make a summary for SREE＇s advantages.展开更多
基金Supported by the National High Technology Research and Development Program of China(863 Program,2009AA011705)the National Natural Science Foundation of China(60903033)
文摘To overcome disadvantages of traditional worst-case execution time （WCET） analysis approaches, we propose a new WCET analysis approach based on independent paths for ARM programs. Based on the results of program flow analysis, it reduces and partitions the control flow graph of the program and obtains a directed graph. Using linear combinations of independent paths of the directed graph, a set of feasible paths can be generated that gives complete coverage in terms of the program paths considered. Their timing measurements and execution counts of program segments are derived from a limited number of measurements of an instrumented version of the program. After the timing measurement of the feasible paths are linearly expressed by the execution times of program seg-ments, a system of equations is derived as a constraint problem, from which we can obtain the execution times of program segments. By assigning the execution times of program segments to weights of edges in the directed graph, the WCET estimate can be calculated on the basis of graph-theoretical techniques. Comparing our WCET estimate with the WCET measurement obtained by the exhaustive measurement, the maximum error ratio is only 8.259 3 %. It is shown that the proposed approach is an effective way to obtain the safe and tight WCET estimate for ARM programs.
基金supported by the University Putra Malaysia and the Ministry of Higher Education Malaysia under grantNumber:(FRGS/1/2023/ICT11/UPM/02/3).
文摘As mobile edge computing continues to develop,the demand for resource-intensive applications is steadily increasing,placing a significant strain on edge nodes.These nodes are normally subject to various constraints,for instance,limited processing capability,a few energy sources,and erratic availability being some of the common ones.Correspondingly,these problems require an effective task allocation algorithmto optimize the resources through continued high system performance and dependability in dynamic environments.This paper proposes an improved Particle Swarm Optimization technique,known as IPSO,for multi-objective optimization in edge computing to overcome these issues.To this end,the IPSO algorithm tries to make a trade-off between two important objectives,which are energy consumption minimization and task execution time reduction.Because of global optimal position mutation and dynamic adjustment to inertia weight,the proposed optimization algorithm can effectively distribute tasks among edge nodes.As a result,it reduces the execution time of tasks and energy consumption.In comparative assessments carried out by IPSO with benchmark methods such as Energy-aware Double-fitness Particle Swarm Optimization(EADPSO)and ICBA,IPSO provides better results than these algorithms.For the maximum task size,when compared with the benchmark methods,IPSO reduces the execution time by 17.1%and energy consumption by 31.58%.These results allow the conclusion that IPSO is an efficient and scalable technique for task allocation at the edge environment.It provides peak efficiency while handling scarce resources and variable workloads.
基金supported by CHB Project "Unstructured Data Management System" under Grant No.2010ZX01042-002-003
文摘As data volume grows, many enterprises are considering using MapReduce for its simplicity. However, how to evaluate the performance improvement before deployment is still an issue. Current researches of MapReduce performance are mainly based on monitoring and simulation, and lack mathematical models. In this paper, we present a simple but powerful performance model for the prediction of the execution time of a MapReduce program with limited resources. We study each component of MapReduce framework, and analyze the relation between the overall performance and the number of mappers and reducers based on our model. Two typical MapReduce programs are evaluated in a small cluster with 13 nodes. Experimental results show that the mathematical performance model can estimate the execution time of MapReduce programs reliably. According to our model, number of mappers and reducers can be tuned to form a better execution pipeline and lead to better performance. The model also points out potential bottlenecks of the framework and future improvement.
文摘Consensus of creativity research suggests that the measurement of both originality and valuableness is necessary when designing creativity tasks.However,few studies have emphasized valuableness when exploring underlying neural substrates of creative thinking.The present study employs product-based creativity tasks that measure both originality and valuableness in an exploration of the dynamic relationship between the default mode(DMN),executive control(ECN),and salience(SN)networks through time windows.This methodology highlights relevance,or valuableness,in creativity evaluation as opposed to divergent thinking tasks solely measuring originality.The researchers identified seven brain regions belonging to the ECN,DMN,and SN as regions of interest(ROIs),as well as four representative seeds to analyze functional connectivity in 25 college student participants.Results showed that all of the identified ROIs were involved during the creative task.The insula,precuneus,and ventrolateral prefrontal cortex(vlPFC)remained active across all stages of product-based creative thinking.Moreover,the connectivity analyses revealed varied interaction patterns of DMN,ECN,and SN at different thinking stages.The integrated findings of the whole brain,ROI,and connectivity analyses suggest a trend that the DMN and SN(which relate to bottom-up thinking)attenuate as time proceeds,whereas the vlPFC(which relates to top-down thinking)gets stronger at later stages;these findings reflect the nature of our creativity tasks and decision-making of valuableness in later stages.Based on brain region activation throughout execution of the task,we propose that product-based creative process may include three stages:exploration and association,incubation and insight,and finally,evaluation and decision making.This model provides a thinking frame for further research and classroom instruction.
文摘In many real-time resource-constrained embedded systems, highly-predictable system behavior is a key design requirement. The “time-triggered co-operative” (TTC) scheduling algorithm provides a good match for a wide range of low-cost embedded applications. As a consequence of the resource, timing, and power constraints, the implementation of such algorithm is often far from trivial. Thus, basic implementation of TTC algorithm can result in excessive levels of task jitter which may jeopardize the predictability of many time-critical applications using this algorithm. This paper discusses the main sources of jitter in earlier TTC implementations and develops two alternative implementations – based on the employment of “sandwich delay” (SD) mechanisms – to reduce task jitter in TTC system significantly. In addition to jitter levels at task release times, we also assess the CPU, memory and power requirements involved in practical implementations of the proposed schedulers. The paper concludes that the TTC scheduler implementation using “multiple timer interrupt” (MTI) technique achieves better performance in terms of timing behavior and resource utilization as opposed to the other implementation which is based on a simple SD mechanism. Use of MTI technique is also found to provide a simple solution to “task overrun” problem which may degrade the performance of many TTC systems.
基金Supported by the National Natural Science Foun-dation of China(69873035) the K.C. Wong Education Foundation,Hong Kong,China
文摘The paper presents the embedded real-time software-oriented requirements engineering environment—SREZ. It involves the whole process of software requirements engineering, including the definition, analysis and checking of requirements ,specifications. We first explain the principles of the executable specification language RTRSM. Subsequently, we introduce the main functions of SREE, illustrate the methods and techniques of checking requirements specifications, especially how to perform simulation execution, combining prototyping method with RTRSM and animated representations. At last, we compare the SREE with other requirements specifications methods and make a summary for SREE＇s advantages.
