A flame length optimization scheme is proposed for multi-antenna downlink systems to guarantee diverse delay- bound violation probability constraints. Due to the difficulties of extracting the quality of service （QoS...A flame length optimization scheme is proposed for multi-antenna downlink systems to guarantee diverse delay- bound violation probability constraints. Due to the difficulties of extracting the quality of service （QoS） metrics from the conventional physical-layer channel models, the link-layer models named effective bandwidth and effective capacity are applied to statistically characterize the source traffic patterns and the queuing service dynamics. With these link-layer models, the source traffic process and the channel service process are mapped to certain QoS parameters. The packet delay-bound violation probability constraints are converted into minimum data rate constraints and the optimization problem is thus formulated into simultaneous inequalities. With the assumption of ergodic block-fading channels, the optimal frame lengths of single-user and multiuser systems are calculated respectively by numerical iterative methods. Theoretical analyses and simulation results show that the given delay-bound violation probability constraints are well satisfied with the optimal frame length.展开更多
Decreasing the power supply voltage in dynamic voltage frequency scaling to save power con- sumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fau...Decreasing the power supply voltage in dynamic voltage frequency scaling to save power con- sumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model （PDFM）, which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applica- tions （graphic, video, digital filtering, etc.）, errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excita- tion, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage fre- quency scaling circuits with tolerable error rates.展开更多
基金The National Science and Technology M ajor Project(No.2012ZX03004005-003)the National Natural Science Foundation of China(No.61171081,61201175)the Research Fund of National M obile Communications Research Laboratory of Southeast University(No.2014A03)
文摘A flame length optimization scheme is proposed for multi-antenna downlink systems to guarantee diverse delay- bound violation probability constraints. Due to the difficulties of extracting the quality of service （QoS） metrics from the conventional physical-layer channel models, the link-layer models named effective bandwidth and effective capacity are applied to statistically characterize the source traffic patterns and the queuing service dynamics. With these link-layer models, the source traffic process and the channel service process are mapped to certain QoS parameters. The packet delay-bound violation probability constraints are converted into minimum data rate constraints and the optimization problem is thus formulated into simultaneous inequalities. With the assumption of ergodic block-fading channels, the optimal frame lengths of single-user and multiuser systems are calculated respectively by numerical iterative methods. Theoretical analyses and simulation results show that the given delay-bound violation probability constraints are well satisfied with the optimal frame length.
基金Supported in part by the National Natural Science Foundation of China (No. 60236020)the MCyT and FEDER Projects TEC2010
文摘Decreasing the power supply voltage in dynamic voltage frequency scaling to save power con- sumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model （PDFM）, which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applica- tions （graphic, video, digital filtering, etc.）, errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excita- tion, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage fre- quency scaling circuits with tolerable error rates.
