目前已有文献给出了uBlock分组密码算法的侧信道防护方案,但是这些方案不仅延迟较高,难以适用于低延迟高吞吐场景,而且在毛刺探测模型下缺乏可证明安全性.针对这一问题,本文给出了在毛刺探测模型下具有可证明安全性的uBlock算法的低延...目前已有文献给出了uBlock分组密码算法的侧信道防护方案,但是这些方案不仅延迟较高,难以适用于低延迟高吞吐场景,而且在毛刺探测模型下缺乏可证明安全性.针对这一问题,本文给出了在毛刺探测模型下具有可证明安全性的uBlock算法的低延迟门限实现方案.此外,我们引入了Changing of the Guards技术来避免防护方案在执行过程中需要额外随机数.对于防护方案的安全性,我们用自动化评估工具SILVER验证了S盒的毛刺探测安全性,并用泄露评估技术TVLA(Test Vector Leakage Assessment)验证了防护方案的整个电路的安全性.最后,我们用Design Compiler工具对防护方案的性能消耗情况进行了评估.评估结果显示,与序列化实现方式的uBlock防护方案相比,我们的防护方案的延迟能够减少约95%.展开更多
The rapid proliferation of Internet of Things(IoT)devices necessitates lightweight cryptographic algorithms and their secure physical implementations.Masking,as a provably secure countermeasure against Side-Channel At...The rapid proliferation of Internet of Things(IoT)devices necessitates lightweight cryptographic algorithms and their secure physical implementations.Masking,as a provably secure countermeasure against Side-Channel Attacks(SCA),has been extensively studied in the context of lightweight cryptography algorithms.Currently,some cryptographers have proposed a low-cost Threshold Implementation(TI)of the uBlock algorithm.However,their approach suffers from significant area overhead due to the inefficient serial and pipelined implementation of uBlock’s Pshufb-Xor(PX)network structure.To address this issue,we develop a new serial and pipelined implementation method that optimizes the area of the uBlock algorithm.Based on this optimization,we implement a 2-share TI scheme for uBlock that requires minimal area resources and does not need fresh randomness.Compared to the state-of-the-art appoach,our method reduces slice area by 63.4%on Field Programmable Gate Arrays(FPGA)platform and Gate Equivalent(GE)area by 17.2%on Application-Specific Integrated Circuit(ASIC)platform for the unprotected implementation.For the protected implementation,our method reduces slice area by 41.5%and GE area by 14.0%.Finally,our protection scheme is validated using the automated tool PROLEAD and evaluated with Test Vector Leakage Assessment(TVLA),achieving first-order glitch-extended probing security.展开更多
文摘目前已有文献给出了uBlock分组密码算法的侧信道防护方案,但是这些方案不仅延迟较高,难以适用于低延迟高吞吐场景,而且在毛刺探测模型下缺乏可证明安全性.针对这一问题,本文给出了在毛刺探测模型下具有可证明安全性的uBlock算法的低延迟门限实现方案.此外,我们引入了Changing of the Guards技术来避免防护方案在执行过程中需要额外随机数.对于防护方案的安全性,我们用自动化评估工具SILVER验证了S盒的毛刺探测安全性,并用泄露评估技术TVLA(Test Vector Leakage Assessment)验证了防护方案的整个电路的安全性.最后,我们用Design Compiler工具对防护方案的性能消耗情况进行了评估.评估结果显示,与序列化实现方式的uBlock防护方案相比,我们的防护方案的延迟能够减少约95%.
基金supported by the National Key R&D Program of China(No.2022YFB310380).
文摘The rapid proliferation of Internet of Things(IoT)devices necessitates lightweight cryptographic algorithms and their secure physical implementations.Masking,as a provably secure countermeasure against Side-Channel Attacks(SCA),has been extensively studied in the context of lightweight cryptography algorithms.Currently,some cryptographers have proposed a low-cost Threshold Implementation(TI)of the uBlock algorithm.However,their approach suffers from significant area overhead due to the inefficient serial and pipelined implementation of uBlock’s Pshufb-Xor(PX)network structure.To address this issue,we develop a new serial and pipelined implementation method that optimizes the area of the uBlock algorithm.Based on this optimization,we implement a 2-share TI scheme for uBlock that requires minimal area resources and does not need fresh randomness.Compared to the state-of-the-art appoach,our method reduces slice area by 63.4%on Field Programmable Gate Arrays(FPGA)platform and Gate Equivalent(GE)area by 17.2%on Application-Specific Integrated Circuit(ASIC)platform for the unprotected implementation.For the protected implementation,our method reduces slice area by 41.5%and GE area by 14.0%.Finally,our protection scheme is validated using the automated tool PROLEAD and evaluated with Test Vector Leakage Assessment(TVLA),achieving first-order glitch-extended probing security.
