A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a ph...A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.展开更多
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ...In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.展开更多
A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr...A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.展开更多
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this ...Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.展开更多
There is an increasing interest of using the Programmable arrays for performing different hardware. In this paper we give an alternative approach and the applications of the Programmable Gate Arrays. We show the field...There is an increasing interest of using the Programmable arrays for performing different hardware. In this paper we give an alternative approach and the applications of the Programmable Gate Arrays. We show the field and the domain where they are more adequate and wihch kind of Programmable array is more efficient to apply. The DPGA and the FPGA are both Programmable Gate Array. They have more possibilities then the conventional devices such as 64 bits microprocessor, however a microprocessor coupled with a programmable array has more opportunity and their implementation is increasing. It is impossible to enumerate all possible uses of Programmable Gate Array. However we use the parameters Latency and throughput. Finite State Machine(FSM), control of data path, processor coupled with a programmable array to build up an alternative approach of the devices and their applications.展开更多
A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller th...A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.展开更多
In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-dep...In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.展开更多
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr...The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.展开更多
Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with singl...Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.展开更多
This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)tr...This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automati...The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)展开更多
In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms...In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.展开更多
Despite more than 40 years of development,it remains difficult for optical logic computing to support more than four operands because the high parallelism of light has not been fully exploited in current methods that ...Despite more than 40 years of development,it remains difficult for optical logic computing to support more than four operands because the high parallelism of light has not been fully exploited in current methods that are restrained by inefficient optical nonlinearity and redundant input modulation.In this paper,we propose a large-scale optical programmable logic array(PLA)based on parallel spectrum modulation.By fully exploiting the wavelength resource,an eight-input PLA is experimentally demonstrated with 256 wavelength channels.And it is extended to nine-input PLA through the combination of wavelength’s and spatial dimensions.Based on PLA,many advanced logic functions like 8-256 decoder,4-bit comparator,adder and multiplier,and state machines are first realized in optics.We implement the two-dimensional optical cellular automaton(CA)for what we believe is the first time and run Conway’s Game of Life to simulate the complex evolutionary processes(pulsar explosion,glider gun,and breeder).Other CA models,such as the replicator-like evolution and the nonisotropic evolution to generate the Sierpinski triangle are also demonstrated.Our work significantly alleviates the challenge of scalability in optical logic devices and provides a universal optical computing platform for two-dimensional CA.展开更多
In order to accommodate the variety of algorithms with different performance in specific application and improve power efficiency,reconfigurable architecture has become an effective methodology in academia and industr...In order to accommodate the variety of algorithms with different performance in specific application and improve power efficiency,reconfigurable architecture has become an effective methodology in academia and industry.However,existing architectures suffer from performance bottleneck due to slow updating of contexts and inadequate flexibility.This paper presents an H-tree based reconfiguration mechanism(HRM)with Huffman-coding-like and mask addressing method in a homogeneous processing element(PE)array,which supports both programmable and data-driven modes.The proposed HRM can transfer reconfiguration instructions/contexts to a particular PE or associated PEs simultaneously in one clock cycle in unicast,multicast and broadcast mode,and shut down the unnecessary PE/PEs according to the current configuration.To verify the correctness and efficiency,we implement it in RTL synthesis and FPGA prototype.Compared to prior works,the experiment results show that the HRM has improved the work frequency by an average of 23.4%,increased the updating speed by 2×,and reduced the area by 36.9%;HRM can also power off the unnecessary PEs which reduced 51%of dynamic power dissipation in certain application configuration.Furthermore,in the data-driven mode,the system frequency can reach 214 MHz,which is 1.68×higher compared with the programmable mode.展开更多
With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutio...With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutional code used is(3,1,7),and the design of a low power Viterbi decoder adapted to multi-rate variations is proposed.In the traditional Viterbi decoding method,the high complexity of path metric(PM)accumulation and Euclidean distance computation leads to the problems of low efficiency and large storage resources in the decoder.In this paper,an improved add compare select(ACS)algorithm,a generalized formula for branch metric(BM)based on Manhattan distance,and a method to reduce the accumulated PM for different Viterbi decoders are put forward.A simulation environment based on Vivado and Matlab to verify the accuracy and effectiveness of the proposed Viterbi decoder is also established.The experimental results show that the total power consumption is reduced by 15.58%while the decoding accuracy of the Viterbi decoder is guaranteed,which meets the design requirements of a low power Viterbi decoder.展开更多
Taking the advantage of ultrafast optical linear and nonlinear effects, all-optical signal processing(AOSP) enables manipulation, regeneration, and computing of information directly in optical domain without resorting...Taking the advantage of ultrafast optical linear and nonlinear effects, all-optical signal processing(AOSP) enables manipulation, regeneration, and computing of information directly in optical domain without resorting to electronics. As a promising photonic integration platform, silicon-on-insulator(SOI) has the advantage of complementary metal oxide semiconductor(CMOS) compatibility, low-loss, compact size as well as large optical nonlinearities. In this paper, we review the recent progress in the project granted to develop silicon-based reconfigurable AOSP chips, which aims to combine the merits of AOSP and silicon photonics to solve the unsustainable cost and energy challenges in future communication and big data applications. Three key challenges are identified in this project:(1) how to finely manipulate and reconfigure optical fields,(2) how to achieve ultra-low loss integrated silicon waveguides and significant enhancement of nonlinear effects,(3) how to mitigate crosstalk between optical, electrical and thermal components. By focusing on these key issues, the following major achievements are realized during the project. First, ultra-low loss silicon-based waveguides as well as ultra-high quality microresonators are developed by advancing key fabrication technologies as well as device structures. Integrated photonic filters with bandwidth and free spectral range reconfigurable in a wide range were realized to finely manipulate and select input light fields with a high degree of freedom. Second, several mechanisms and new designs that aim at nonlinear enhancement have been proposed, including optical ridge waveguides with reverse biased PIN junction, slot waveguides,multimode waveguides and parity-time symmetry coupled microresonators. Advanced AOSP operations are verified with these novel designs. Logical computations at 100 Gbit/s were demonstrated with self-developed, monolithic integrated programmable optical logic array. High-dimensional multi-value logic operations based on the four-wave mixing effect are realized. Multi-channel all-optical amplitude and phase regeneration technology is developed, and a multi-channel, multiformat, reconfigurable all-optical regeneration chip is realized. Expanding regeneration capacity via spatial dimension is also verified. Third, the crosstalk from optical as well as thermal coupling due to high-density integration are mitigated by developing novel optical designs and advanced packaging technologies, enabling high-density, small size, multi-channel and multi-functional operation with low power consumption. Finally, four programmable AOSP chips are developed, i.e.,programmable photonic filter chip, programmable photonic logic operation chip, multi-dimensional all-optical regeneration chip, and multi-channel and multi-functional AOSP chip with packaging. The major achievements developed in this project pave the way toward ultra-low loss, high-speed, high-efficient, high-density information processing in future classical and non-classical communication and computing applications.展开更多
基金The National Natural Science Foundation of China(No.62401168,62401139,62401170)China Postdoctoral Science Foundation(No.2023MD744197)+2 种基金Postdoctoral Fellowship Program of CPSF(No.GZC20230631)Project for Enhancing Young and Middle-aged Teacher’s Research Basis Ability in Colleges of Guangxi(No.2023KY0218)Guangxi Key Laboratory Foundation of Optoelectronic Information Processing(No.GD23102)。
文摘A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.
基金Science &Technology Plan Foundation of Hunan Province,China(No.2010F3102)Science Research Foundation of Hunan Province,China(No.08C392)
文摘In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.
基金the Natural Science Foundation of Hubei Province (No.2005ABA301)
文摘A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
文摘Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.
文摘There is an increasing interest of using the Programmable arrays for performing different hardware. In this paper we give an alternative approach and the applications of the Programmable Gate Arrays. We show the field and the domain where they are more adequate and wihch kind of Programmable array is more efficient to apply. The DPGA and the FPGA are both Programmable Gate Array. They have more possibilities then the conventional devices such as 64 bits microprocessor, however a microprocessor coupled with a programmable array has more opportunity and their implementation is increasing. It is impossible to enumerate all possible uses of Programmable Gate Array. However we use the parameters Latency and throughput. Finite State Machine(FSM), control of data path, processor coupled with a programmable array to build up an alternative approach of the devices and their applications.
基金Project supported by the Second Stage of Brain Korea 21 Projectssupported by Industrial Strategic Technology Development Program funded by the Ministry of Knowledge Economy (MKE,Korea)(10039239,"Development of Power Management System SoC Supporting Multi-Battery-Cells and Multi-Energy-Sources for Smart Phones and Smart Devices")
文摘A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.
文摘In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.
基金Supported by the CAS/SAFEA International Partnership Program for Creative Research Teams,National High Technology Research and Develop Program of China(2012AA012301)National Science and Technology Major Project of China(2013ZX03006004)
文摘The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.
基金Supported by the Commission of Science Technology and Industry for National Defense and the National Natural Science Foundation of China (No. 90307011)
文摘Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.
基金This work was supported in part by the Geran Galakan Penyelidik Muda Grant(GGPM),Universiti Kebangsaan Malaysia,Selangor,Malaysia under grant GGPM-2021-055.
文摘This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
文摘The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)
基金Guangdong Province Science and Technology Guiding Project(2005B10101013)
文摘In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.
基金supported in part by the National Key Research and Development Program of China(Grant No.2022YFB2804203)the National Natural Science Foundation of China(Grant Nos.62075075,62275088)the Knowledge Innovation Program of Wuhan-Basic Research(Grant No.2023010201010049).
文摘Despite more than 40 years of development,it remains difficult for optical logic computing to support more than four operands because the high parallelism of light has not been fully exploited in current methods that are restrained by inefficient optical nonlinearity and redundant input modulation.In this paper,we propose a large-scale optical programmable logic array(PLA)based on parallel spectrum modulation.By fully exploiting the wavelength resource,an eight-input PLA is experimentally demonstrated with 256 wavelength channels.And it is extended to nine-input PLA through the combination of wavelength’s and spatial dimensions.Based on PLA,many advanced logic functions like 8-256 decoder,4-bit comparator,adder and multiplier,and state machines are first realized in optics.We implement the two-dimensional optical cellular automaton(CA)for what we believe is the first time and run Conway’s Game of Life to simulate the complex evolutionary processes(pulsar explosion,glider gun,and breeder).Other CA models,such as the replicator-like evolution and the nonisotropic evolution to generate the Sierpinski triangle are also demonstrated.Our work significantly alleviates the challenge of scalability in optical logic devices and provides a universal optical computing platform for two-dimensional CA.
基金supported by the National Natural Science Foundation of China (Nos. 61834005, 61602377, 61772417, 61802304, 61874087)the Shaanxi International Science and Technology Cooperation Program No. 2018KW-006+1 种基金Shaanxi Provincial Key R&D Plan under Grant No. 2017GY-060Shaanxi Province Co-ordination Innovation Project of Science and Technology under Grant No. 2016KTZDGY02-04-02
文摘In order to accommodate the variety of algorithms with different performance in specific application and improve power efficiency,reconfigurable architecture has become an effective methodology in academia and industry.However,existing architectures suffer from performance bottleneck due to slow updating of contexts and inadequate flexibility.This paper presents an H-tree based reconfiguration mechanism(HRM)with Huffman-coding-like and mask addressing method in a homogeneous processing element(PE)array,which supports both programmable and data-driven modes.The proposed HRM can transfer reconfiguration instructions/contexts to a particular PE or associated PEs simultaneously in one clock cycle in unicast,multicast and broadcast mode,and shut down the unnecessary PE/PEs according to the current configuration.To verify the correctness and efficiency,we implement it in RTL synthesis and FPGA prototype.Compared to prior works,the experiment results show that the HRM has improved the work frequency by an average of 23.4%,increased the updating speed by 2×,and reduced the area by 36.9%;HRM can also power off the unnecessary PEs which reduced 51%of dynamic power dissipation in certain application configuration.Furthermore,in the data-driven mode,the system frequency can reach 214 MHz,which is 1.68×higher compared with the programmable mode.
基金Supported by the National Natural Science Foundation of China(No.62103257).
文摘With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutional code used is(3,1,7),and the design of a low power Viterbi decoder adapted to multi-rate variations is proposed.In the traditional Viterbi decoding method,the high complexity of path metric(PM)accumulation and Euclidean distance computation leads to the problems of low efficiency and large storage resources in the decoder.In this paper,an improved add compare select(ACS)algorithm,a generalized formula for branch metric(BM)based on Manhattan distance,and a method to reduce the accumulated PM for different Viterbi decoders are put forward.A simulation environment based on Vivado and Matlab to verify the accuracy and effectiveness of the proposed Viterbi decoder is also established.The experimental results show that the total power consumption is reduced by 15.58%while the decoding accuracy of the Viterbi decoder is guaranteed,which meets the design requirements of a low power Viterbi decoder.
基金supported by the National Key Research and Development Program of China(No.2019YFB2203100).
文摘Taking the advantage of ultrafast optical linear and nonlinear effects, all-optical signal processing(AOSP) enables manipulation, regeneration, and computing of information directly in optical domain without resorting to electronics. As a promising photonic integration platform, silicon-on-insulator(SOI) has the advantage of complementary metal oxide semiconductor(CMOS) compatibility, low-loss, compact size as well as large optical nonlinearities. In this paper, we review the recent progress in the project granted to develop silicon-based reconfigurable AOSP chips, which aims to combine the merits of AOSP and silicon photonics to solve the unsustainable cost and energy challenges in future communication and big data applications. Three key challenges are identified in this project:(1) how to finely manipulate and reconfigure optical fields,(2) how to achieve ultra-low loss integrated silicon waveguides and significant enhancement of nonlinear effects,(3) how to mitigate crosstalk between optical, electrical and thermal components. By focusing on these key issues, the following major achievements are realized during the project. First, ultra-low loss silicon-based waveguides as well as ultra-high quality microresonators are developed by advancing key fabrication technologies as well as device structures. Integrated photonic filters with bandwidth and free spectral range reconfigurable in a wide range were realized to finely manipulate and select input light fields with a high degree of freedom. Second, several mechanisms and new designs that aim at nonlinear enhancement have been proposed, including optical ridge waveguides with reverse biased PIN junction, slot waveguides,multimode waveguides and parity-time symmetry coupled microresonators. Advanced AOSP operations are verified with these novel designs. Logical computations at 100 Gbit/s were demonstrated with self-developed, monolithic integrated programmable optical logic array. High-dimensional multi-value logic operations based on the four-wave mixing effect are realized. Multi-channel all-optical amplitude and phase regeneration technology is developed, and a multi-channel, multiformat, reconfigurable all-optical regeneration chip is realized. Expanding regeneration capacity via spatial dimension is also verified. Third, the crosstalk from optical as well as thermal coupling due to high-density integration are mitigated by developing novel optical designs and advanced packaging technologies, enabling high-density, small size, multi-channel and multi-functional operation with low power consumption. Finally, four programmable AOSP chips are developed, i.e.,programmable photonic filter chip, programmable photonic logic operation chip, multi-dimensional all-optical regeneration chip, and multi-channel and multi-functional AOSP chip with packaging. The major achievements developed in this project pave the way toward ultra-low loss, high-speed, high-efficient, high-density information processing in future classical and non-classical communication and computing applications.
