A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and sin...A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.展开更多
The in-phase and quadrature-phase imbalance (IQI) is one of the major radio frequency impairments existing in orthogonal frequency division multiplexing (OFDM) systems with direct-conversion transceivers. During the t...The in-phase and quadrature-phase imbalance (IQI) is one of the major radio frequency impairments existing in orthogonal frequency division multiplexing (OFDM) systems with direct-conversion transceivers. During the transmission of the communication signal, the impact of IQI is coupled with channel impulse responses (CIR), which makes the traditional channel estimation schemes ineffective. A decoupled estimation scheme is proposed to separately estimate the frequency-dependent IQI and wireless channel. Firstly, the generalized channel model is built to separate the parameters of IQI and wireless channel. Then an iterative estimation scheme of frequency-dependent IQI is designed at the initial stage of communication. Finally, based on the estimation result of IQI, the least square algorithm is utilized to estimate the channel-related parameters at each time of channel variation. Compared with the joint estimation schemes of IQI and channel, the proposed decoupled estimation scheme requires much lower training overhead at each time of channel variation. Simulation results demonstrate the good estimation performance of the proposed scheme.展开更多
In this paper,a general scheme in digital self-interference cancellation at baseband for zero-IF full-duplex transceivers is presented. We model the self-interference signals specifically with only the nonlinear disto...In this paper,a general scheme in digital self-interference cancellation at baseband for zero-IF full-duplex transceivers is presented. We model the self-interference signals specifically with only the nonlinear distortion signals falling in receiving band considered. A joint estimation algorithm is proposed for compensating the time delay and frequency offset taking into account the IQ amplitude and phase imbalances from mixers. The memory effect and nonlinear distortion are adaptively estimated by the de-correlated normalized least mean square(DNLMS) algorithm. Numerical simulation results demonstrate that the proposed self-interference cancellation scheme can efficiently compensate the self-interference and outperform the existing traditional solutions.展开更多
Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoele...Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoelectronics transceivers in DCs,as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process.We also summarize the research on the main components in silicon photonic transceivers.In particular,quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts.Some of the solutions for highspeed optical interconnection in DCs are then discussed.Among them,wavelength division multiplexing and four-level pulseamplitude modulation have been widely studied and applied.At present,the application of coherent optical communication technology has moved from the backbone network,to the metro network,and then to DCs.展开更多
The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of...The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.展开更多
To improve the quality of the illumination distribution,one novel indoor visible light communication(VLC)system,which is jointly assisted by the angle-diversity transceivers and simultaneous transmission and reflectio...To improve the quality of the illumination distribution,one novel indoor visible light communication(VLC)system,which is jointly assisted by the angle-diversity transceivers and simultaneous transmission and reflection-intelligent reflecting surface(STAR-IRS),has been proposed in this work.A Harris Hawks optimizer algorithm(HHOA)-based two-stage alternating iteration algorithm(TSAIA)is presented to jointly optimize the magnitude and uniformity of the received optical power.Besides,to demonstrate the superiority of the proposed strategy,several benchmark schemes are simulated and compared.Results showed that compared to other optimization strategies,the TSAIA scheme is more capable of balancing the average value and variance of the received optical power,when the maximal ratio combining(MRC)strategy is adopted at the receiver.Moreover,as the number of the STAR-IRS elements increases,the optical power variance of the system optimized by TSAIA scheme would become smaller while the average optical power would get larger.This study will benefit the design of received optical power distribution for indoor VLC systems.展开更多
The combining microelectronic devices and associated technologies onto a single silicon chip poses a substantial challenge.However,in recent years,the area of silicon photonics has experienced remarkable advancements ...The combining microelectronic devices and associated technologies onto a single silicon chip poses a substantial challenge.However,in recent years,the area of silicon photonics has experienced remarkable advancements and notable leaps in performance.The performance of silicon on insulator(SOI)based photonic devices,such as fast silicon optical modulators,photonic transceivers,optical filters,etc.,have been discussed.This would be a step forward in creating standalone silicon photonic devices,strengthening the possibility of single on-chip nanophotonic integrated circuits.Suppose an integrated silicon photonic chip is designed and fabricated.In that case,it might drastically modify these combined photonic component costs,power consumption,and size,bringing substantial,perhaps revolutionary,changes to the next-generation communications sector.Yet,the monolithic integration of photonic and electrical circuitry is a significant technological difficulty.A complicated set of factors must be carefully considered to determine which application will have the best chance of success employing silicon-based integrated product solutions.The processing limitations connected to the current process flow,the process generation(sometimes referred to as lithography node generation),and packaging requirements are a few of these factors to consider.This review highlights recent developments in integrated silicon photonic devices and their proven applications,including but not limited to photonic waveguides,photonic amplifiers and filters,onchip photonic transceivers,and the state-of-the-art of silicon photonic in multidimensional quantum systems.The investigated devices aim to expedite the transfer of silicon photonics from academia to industry by opening the next phase in on-chip silicon photonics and enabling the application of silicon photonic-based devices in various optical systems.展开更多
The Ultra-WideBand(UWB) technique, which offers good energy efficiency, flexible data rate, and high ranging accuracy, has recently been recognized as a revived wireless technology for short distance communication.Thi...The Ultra-WideBand(UWB) technique, which offers good energy efficiency, flexible data rate, and high ranging accuracy, has recently been recognized as a revived wireless technology for short distance communication.This paper presents a brief overview of two UWB techniques, covering Impulse-Radio UWB(IR-UWB) and FrequencyModulation UWB(FM-UWB) methods. The link margin enhancement technique, Very-WideBand(VWB), and power consumption reducing technique, chirp UWB, are also introduced. Then, several potential applications of IR-UWB with transceiver architectures are addressed, including high data rate proximity communication and secure wireless connectivity. With fine-ranging and energy-efficient communication features, the UWB wireless technology is highly promising for secure mobile Internet of Things(IoT) applications.展开更多
The paper describes a low-power CMOS voltage-controlled oscillator (VCO) with dual-band local oscillating (LO) signal outputs for 5/2.5-GHz wireless local area network (WLAN) transceivers. The VCO is based on an on-ch...The paper describes a low-power CMOS voltage-controlled oscillator (VCO) with dual-band local oscillating (LO) signal outputs for 5/2.5-GHz wireless local area network (WLAN) transceivers. The VCO is based on an on-chip symmetrical spiral inductor and a differential varactor. The 2.5-GHz quadrature LO signals are generated using the injection-locked frequency divider (ILFD) technique. The ILFD structure is similar to the VCO structure with its wide tracking range. The design tool ASITIC was used to optimize all on-chip symmetrical inductors. The power consumption was kept low with differential LC tanks and the ILFD technique. The circuit was implemented in a 0.18-μm CMOS process. Hspice and SpectreRF simulations show the proposed circuit could generate low phase noise 5/2.5-GHz dual band LO signals with a wide tuning range. The 2.5-GHz LO signals are quadrature with almost no phase and amplitude errors. The circuit consumes less than 5.3 mW in the tuning range with a power supply voltage of 1.5 V. The die area is only 1.0 mm×1.0 mm.展开更多
A monolithic integration of the light emitting diode(LED)and photodetector(PD)based onⅢ-nitride is designed and fabricated on a sapphire substrate to act as a transceiver.Due to the coexistence of light emission and ...A monolithic integration of the light emitting diode(LED)and photodetector(PD)based onⅢ-nitride is designed and fabricated on a sapphire substrate to act as a transceiver.Due to the coexistence of light emission and detection phenomenon of the multi-quantum well(MQW)structure,the monolithic transceiver can effectively sense environmental changes.By integrating a deformable Polydimethylsiloxane(PDMS)film on the transceiver chip,external force variation can be effectively detected.As the thickness of the PDMS reduces,the sensitivity significantly improves but at the expense of the measuring range.A sensitivity of 2.9683%per newton for a range of 0-11 N is obtained when a 2 mm-thick PDMS film is packaged.The proposed monolithic GaN transceiver-based sensing system has the advantages of compactness,low cost,and simple assembly,providing an optional method for practical applications.展开更多
The challenges in the design of CMOS millimeter-wave （mm-wave） transceiver for Gbps wireless com- munication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide ...The challenges in the design of CMOS millimeter-wave （mm-wave） transceiver for Gbps wireless com- munication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the band- width expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier （PA） and self-healing technique are introduced to improve the PA＇s average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers.展开更多
This paper considers a massive single-input multiple-output(SIMO)system,where multiple singleantenna transmitters simultaneously communicate with a receiver equipped with a large number of antennas.Different from the ...This paper considers a massive single-input multiple-output(SIMO)system,where multiple singleantenna transmitters simultaneously communicate with a receiver equipped with a large number of antennas.Different from the conventional noncoherent transceivers which require a certain level of the statistical information on the channel fading,we propose a joint transceiver design method based on machine learning,requiring a limited number of channel realizations.In the proposed method,the multiple transmitters,the channel,and the receiver are represented with a deep neural network(NN),and an autoencoder is adopted to minimize the end-to-end transmission error probability.Besides,the relationship between the number of training samples and the transmission error probability is analyzed based on the confidence interval method.Simulation results show that the proposed NN-based transceiver achieves lower transmission error probability in typical scenarios,and is more robust against the channel parameters variation compared with the existing methods.展开更多
With the explosive development of artificial intelligence(AI),machine learning(ML),and high-performance comput-ing(HPC),the ever-growing data movement is asking for high density interconnects with higher bandwidth(BW)...With the explosive development of artificial intelligence(AI),machine learning(ML),and high-performance comput-ing(HPC),the ever-growing data movement is asking for high density interconnects with higher bandwidth(BW),lower power and lower latency[1−3].The optical I/O leverages silicon photonic(SiPh)technology to enable high-density large-scale integrated photonics.展开更多
A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-fo...A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.展开更多
This article presents an 8-element dual-polarized phased-array transceiver(TRX)front-end IC for millimeter-wave(mm-Wave)5G new radio(NR).Power enhancement technologies for power amplifiers(PA)in mm-Wave 5G phased-arra...This article presents an 8-element dual-polarized phased-array transceiver(TRX)front-end IC for millimeter-wave(mm-Wave)5G new radio(NR).Power enhancement technologies for power amplifiers(PA)in mm-Wave 5G phased-array TRX are discussed.A four-stage wideband high-power class-AB PA with distributed-active-transformer(DAT)power combining and multi-stage second-harmonic traps is proposed,ensuring the mitigated amplitude-to-phase(AM-PM)distortions across wide carrier frequencies without degrading transmitting(TX)power,gain and efficiency.TX and receiving(RX)switching is achieved by a matching network co-designed on-chip T/R switch.In each TRX element,6-bit 360°phase shifting and 6-bit 31.5-dB gain tuning are respectively achieved by the digital-controlled vector-modulated phase shifter(VMPS)and differential attenuator(ATT).Fabricated in 65-nm bulk complementary metal oxide semiconductor(CMOS),the proposed TRX demonstrates the measured peak TX/RX gains of 25.5/21.3 dB,covering the 24−29.5 GHz band.The measured peak TX OP1dB and power-added efficiency(PAE)are 20.8 dBm and 21.1%,respectively.The measured minimum RX NF is 4.1 dB.The TRX achieves an output power of 11.0−12.4 dBm and error vector magnitude(EVM)of 5%with 400-MHz 5G NR FR2 OFDM 64-QAM signals across 24−29.5 GHz,covering 3GPP 5G NR FR2 operating bands of n257,n258,and n261.展开更多
The in-band full-duplex(IBFD)wireless system is a promising candidate for 6G and beyond,as it can double data throughput and enormously lower transmission latency by supporting simultaneous in-band transmission and re...The in-band full-duplex(IBFD)wireless system is a promising candidate for 6G and beyond,as it can double data throughput and enormously lower transmission latency by supporting simultaneous in-band transmission and reception of signals.Enabling IBFD systems requires a substantial mitigation of a transmitter(Tx)’s strong self-interference(SI)signal into the receiver(Rx)channel.However,current state-ofthe-art approaches to tackle this challenge are inefficient in terms of performance,cost,and complexity,hindering the commercialization of IBFD techniques.In this work,we devise and demonstrate an innovative approach to realize IBFD systems that exhibit superior performance with a low-cost and lesscomplex architecture in an all-passive module.Our scheme is based on meticulously combining polarization-division multiplexing(PDM)with ferromagnetic nonreciprocity to achieve ultra-high isolation between Tx and Rx channels.Such an unprecedented conception has become feasible thanks to a concurrent dual-mode circulator—a new component introduced for the first time—as a key feature of our module,and a dual-mode waveguide that transforms two orthogonally polarized waves into two orthogonal waveguide modes.In addition,we propose a unique passive tunable secondary SI cancellation(SIC)mechanism,which is embedded within the proposed module and boosts the isolation over a relatively broad bandwidth.We report,solely in the analog domain,experimental isolation levels of 50,70,and 80 dB over 340,101,and 33 MHz bandwidth at the center frequency of interest,respectively,with excellent tuning capability.Furthermore,the module is tested in two real IBFD scenarios to assess its performance in connection with Tx-to-Rx leakage and modulation error in the presence of a Tx’s strong interference signal.展开更多
An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are b...An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.展开更多
The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band an...The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.展开更多
文摘A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.
基金supported by the National Natural Science Foundation of China(6140123261471200+4 种基金6150124861501254)the China Postdoctoral Science Foundation(2014M561692)the Jiangsu Province Postdoctoral Science Foundation(1402087C)the NUPTSF(NY213063)
文摘The in-phase and quadrature-phase imbalance (IQI) is one of the major radio frequency impairments existing in orthogonal frequency division multiplexing (OFDM) systems with direct-conversion transceivers. During the transmission of the communication signal, the impact of IQI is coupled with channel impulse responses (CIR), which makes the traditional channel estimation schemes ineffective. A decoupled estimation scheme is proposed to separately estimate the frequency-dependent IQI and wireless channel. Firstly, the generalized channel model is built to separate the parameters of IQI and wireless channel. Then an iterative estimation scheme of frequency-dependent IQI is designed at the initial stage of communication. Finally, based on the estimation result of IQI, the least square algorithm is utilized to estimate the channel-related parameters at each time of channel variation. Compared with the joint estimation schemes of IQI and channel, the proposed decoupled estimation scheme requires much lower training overhead at each time of channel variation. Simulation results demonstrate the good estimation performance of the proposed scheme.
基金supported in part by the National Natural Science Foundation of China(No.61601027)
文摘In this paper,a general scheme in digital self-interference cancellation at baseband for zero-IF full-duplex transceivers is presented. We model the self-interference signals specifically with only the nonlinear distortion signals falling in receiving band considered. A joint estimation algorithm is proposed for compensating the time delay and frequency offset taking into account the IQ amplitude and phase imbalances from mixers. The memory effect and nonlinear distortion are adaptively estimated by the de-correlated normalized least mean square(DNLMS) algorithm. Numerical simulation results demonstrate that the proposed self-interference cancellation scheme can efficiently compensate the self-interference and outperform the existing traditional solutions.
基金supported by the National Key Research and Development Program of China under Grant No.2016YFB 0402302the National Natural Science Foundation of China under Grant No.91433206。
文摘Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoelectronics transceivers in DCs,as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process.We also summarize the research on the main components in silicon photonic transceivers.In particular,quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts.Some of the solutions for highspeed optical interconnection in DCs are then discussed.Among them,wavelength division multiplexing and four-level pulseamplitude modulation have been widely studied and applied.At present,the application of coherent optical communication technology has moved from the backbone network,to the metro network,and then to DCs.
文摘The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.
基金supported by the National Natural Science Foundation of China(No.62071365)the Key Research and Development Program of Shaanxi Province(No.2017ZDCXL-GY-06-02).
文摘To improve the quality of the illumination distribution,one novel indoor visible light communication(VLC)system,which is jointly assisted by the angle-diversity transceivers and simultaneous transmission and reflection-intelligent reflecting surface(STAR-IRS),has been proposed in this work.A Harris Hawks optimizer algorithm(HHOA)-based two-stage alternating iteration algorithm(TSAIA)is presented to jointly optimize the magnitude and uniformity of the received optical power.Besides,to demonstrate the superiority of the proposed strategy,several benchmark schemes are simulated and compared.Results showed that compared to other optimization strategies,the TSAIA scheme is more capable of balancing the average value and variance of the received optical power,when the maximal ratio combining(MRC)strategy is adopted at the receiver.Moreover,as the number of the STAR-IRS elements increases,the optical power variance of the system optimized by TSAIA scheme would become smaller while the average optical power would get larger.This study will benefit the design of received optical power distribution for indoor VLC systems.
文摘The combining microelectronic devices and associated technologies onto a single silicon chip poses a substantial challenge.However,in recent years,the area of silicon photonics has experienced remarkable advancements and notable leaps in performance.The performance of silicon on insulator(SOI)based photonic devices,such as fast silicon optical modulators,photonic transceivers,optical filters,etc.,have been discussed.This would be a step forward in creating standalone silicon photonic devices,strengthening the possibility of single on-chip nanophotonic integrated circuits.Suppose an integrated silicon photonic chip is designed and fabricated.In that case,it might drastically modify these combined photonic component costs,power consumption,and size,bringing substantial,perhaps revolutionary,changes to the next-generation communications sector.Yet,the monolithic integration of photonic and electrical circuitry is a significant technological difficulty.A complicated set of factors must be carefully considered to determine which application will have the best chance of success employing silicon-based integrated product solutions.The processing limitations connected to the current process flow,the process generation(sometimes referred to as lithography node generation),and packaging requirements are a few of these factors to consider.This review highlights recent developments in integrated silicon photonic devices and their proven applications,including but not limited to photonic waveguides,photonic amplifiers and filters,onchip photonic transceivers,and the state-of-the-art of silicon photonic in multidimensional quantum systems.The investigated devices aim to expedite the transfer of silicon photonics from academia to industry by opening the next phase in on-chip silicon photonics and enabling the application of silicon photonic-based devices in various optical systems.
基金supported in part by the National Natural Science Foundation of China (No. 61774092)。
文摘The Ultra-WideBand(UWB) technique, which offers good energy efficiency, flexible data rate, and high ranging accuracy, has recently been recognized as a revived wireless technology for short distance communication.This paper presents a brief overview of two UWB techniques, covering Impulse-Radio UWB(IR-UWB) and FrequencyModulation UWB(FM-UWB) methods. The link margin enhancement technique, Very-WideBand(VWB), and power consumption reducing technique, chirp UWB, are also introduced. Then, several potential applications of IR-UWB with transceiver architectures are addressed, including high data rate proximity communication and secure wireless connectivity. With fine-ranging and energy-efficient communication features, the UWB wireless technology is highly promising for secure mobile Internet of Things(IoT) applications.
文摘The paper describes a low-power CMOS voltage-controlled oscillator (VCO) with dual-band local oscillating (LO) signal outputs for 5/2.5-GHz wireless local area network (WLAN) transceivers. The VCO is based on an on-chip symmetrical spiral inductor and a differential varactor. The 2.5-GHz quadrature LO signals are generated using the injection-locked frequency divider (ILFD) technique. The ILFD structure is similar to the VCO structure with its wide tracking range. The design tool ASITIC was used to optimize all on-chip symmetrical inductors. The power consumption was kept low with differential LC tanks and the ILFD technique. The circuit was implemented in a 0.18-μm CMOS process. Hspice and SpectreRF simulations show the proposed circuit could generate low phase noise 5/2.5-GHz dual band LO signals with a wide tuning range. The 2.5-GHz LO signals are quadrature with almost no phase and amplitude errors. The circuit consumes less than 5.3 mW in the tuning range with a power supply voltage of 1.5 V. The die area is only 1.0 mm×1.0 mm.
基金supported by the National Key Research and Development Program under Grant No.2024YFE0204700Natural Science Foundation of Jiangsu Province under Grant No.BG2024023Higher Education Discipline Innovation Project under Grant No.D17018。
文摘A monolithic integration of the light emitting diode(LED)and photodetector(PD)based onⅢ-nitride is designed and fabricated on a sapphire substrate to act as a transceiver.Due to the coexistence of light emission and detection phenomenon of the multi-quantum well(MQW)structure,the monolithic transceiver can effectively sense environmental changes.By integrating a deformable Polydimethylsiloxane(PDMS)film on the transceiver chip,external force variation can be effectively detected.As the thickness of the PDMS reduces,the sensitivity significantly improves but at the expense of the measuring range.A sensitivity of 2.9683%per newton for a range of 0-11 N is obtained when a 2 mm-thick PDMS film is packaged.The proposed monolithic GaN transceiver-based sensing system has the advantages of compactness,low cost,and simple assembly,providing an optional method for practical applications.
基金Project supported in part by the National Natural Science Foundation of China(No.61331003)
文摘The challenges in the design of CMOS millimeter-wave （mm-wave） transceiver for Gbps wireless com- munication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the band- width expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier （PA） and self-healing technique are introduced to improve the PA＇s average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers.
基金The work was supported in part by the Key Area R&D Program of Guangdong Province with Grant No.2018B030338001by the National Key R&D Program of China with Grant No.2018YFB1800800+2 种基金y Natural Science Foundation of China with grant NSFC-61629101by Guangdong Research Project No.2017ZT07X152by Shenzhen Key Lab Fund No.ZDSYS201707251409055.
文摘This paper considers a massive single-input multiple-output(SIMO)system,where multiple singleantenna transmitters simultaneously communicate with a receiver equipped with a large number of antennas.Different from the conventional noncoherent transceivers which require a certain level of the statistical information on the channel fading,we propose a joint transceiver design method based on machine learning,requiring a limited number of channel realizations.In the proposed method,the multiple transmitters,the channel,and the receiver are represented with a deep neural network(NN),and an autoencoder is adopted to minimize the end-to-end transmission error probability.Besides,the relationship between the number of training samples and the transmission error probability is analyzed based on the confidence interval method.Simulation results show that the proposed NN-based transceiver achieves lower transmission error probability in typical scenarios,and is more robust against the channel parameters variation compared with the existing methods.
基金This work was supported by the National Natural Science Foundation of China(Grant Nos.61925505,92373209 and 62235017).
文摘With the explosive development of artificial intelligence(AI),machine learning(ML),and high-performance comput-ing(HPC),the ever-growing data movement is asking for high density interconnects with higher bandwidth(BW),lower power and lower latency[1−3].The optical I/O leverages silicon photonic(SiPh)technology to enable high-density large-scale integrated photonics.
基金supported by National Natural Science Foundation of China under Grant 62174132the Fundamental Research Funds for Central Universities under Grant xzy022022060.
文摘A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.
基金This work was supported in part by the National Key Research and Development Program of China under Grant 2019YFB1803000in part by the Major Key Project of Peng Cheng Laboratory,Shenzhen,China,under Project PCL2021A01-2.
文摘This article presents an 8-element dual-polarized phased-array transceiver(TRX)front-end IC for millimeter-wave(mm-Wave)5G new radio(NR).Power enhancement technologies for power amplifiers(PA)in mm-Wave 5G phased-array TRX are discussed.A four-stage wideband high-power class-AB PA with distributed-active-transformer(DAT)power combining and multi-stage second-harmonic traps is proposed,ensuring the mitigated amplitude-to-phase(AM-PM)distortions across wide carrier frequencies without degrading transmitting(TX)power,gain and efficiency.TX and receiving(RX)switching is achieved by a matching network co-designed on-chip T/R switch.In each TRX element,6-bit 360°phase shifting and 6-bit 31.5-dB gain tuning are respectively achieved by the digital-controlled vector-modulated phase shifter(VMPS)and differential attenuator(ATT).Fabricated in 65-nm bulk complementary metal oxide semiconductor(CMOS),the proposed TRX demonstrates the measured peak TX/RX gains of 25.5/21.3 dB,covering the 24−29.5 GHz band.The measured peak TX OP1dB and power-added efficiency(PAE)are 20.8 dBm and 21.1%,respectively.The measured minimum RX NF is 4.1 dB.The TRX achieves an output power of 11.0−12.4 dBm and error vector magnitude(EVM)of 5%with 400-MHz 5G NR FR2 OFDM 64-QAM signals across 24−29.5 GHz,covering 3GPP 5G NR FR2 operating bands of n257,n258,and n261.
基金supported by a Natural Sciences and Engineering Research Council(NSERC)-sponsored Industrial Research Chair program,an NSERC Discovery Grantin part by the Fonds de recherche du Québec Nature et technologies(FRQNT)Doctoral Fellowship of Amir Afshani funded by the Government of Québec Province.
文摘The in-band full-duplex(IBFD)wireless system is a promising candidate for 6G and beyond,as it can double data throughput and enormously lower transmission latency by supporting simultaneous in-band transmission and reception of signals.Enabling IBFD systems requires a substantial mitigation of a transmitter(Tx)’s strong self-interference(SI)signal into the receiver(Rx)channel.However,current state-ofthe-art approaches to tackle this challenge are inefficient in terms of performance,cost,and complexity,hindering the commercialization of IBFD techniques.In this work,we devise and demonstrate an innovative approach to realize IBFD systems that exhibit superior performance with a low-cost and lesscomplex architecture in an all-passive module.Our scheme is based on meticulously combining polarization-division multiplexing(PDM)with ferromagnetic nonreciprocity to achieve ultra-high isolation between Tx and Rx channels.Such an unprecedented conception has become feasible thanks to a concurrent dual-mode circulator—a new component introduced for the first time—as a key feature of our module,and a dual-mode waveguide that transforms two orthogonally polarized waves into two orthogonal waveguide modes.In addition,we propose a unique passive tunable secondary SI cancellation(SIC)mechanism,which is embedded within the proposed module and boosts the isolation over a relatively broad bandwidth.We report,solely in the analog domain,experimental isolation levels of 50,70,and 80 dB over 340,101,and 33 MHz bandwidth at the center frequency of interest,respectively,with excellent tuning capability.Furthermore,the module is tested in two real IBFD scenarios to assess its performance in connection with Tx-to-Rx leakage and modulation error in the presence of a Tx’s strong interference signal.
文摘An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.
基金The National Natural Science Foundation of China (No.60702027,60921063)the National Basic Research Program of China(973 Program)(No.2010CB327400)the National Science and Technology Major Project of Ministry of Science and Technology of China(No.2010ZX03007-001-01,2011ZX03004-001)
文摘The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.
