The space-air-ground integrated network(SAGIN)combines the superiority of the satellite,aerial,and ground communications,which is envisioned to provide high-precision positioning ability as well as seamless connectivi...The space-air-ground integrated network(SAGIN)combines the superiority of the satellite,aerial,and ground communications,which is envisioned to provide high-precision positioning ability as well as seamless connectivity in the 5G and Beyond 5G(B5G)systems.In this paper,we propose a three-dimensional SAGIN localization scheme for ground agents utilizing multi-source information from satellites,base stations and unmanned aerial vehicles(UAVs).Based on the designed scheme,we derive the positioning performance bound and establish a distributed maximum likelihood algorithm to jointly estimate the positions and clock offsets of ground agents.Simulation results demonstrate the validity of the SAGIN localization scheme and reveal the effects of the number of satellites,the number of base stations,the number of UAVs and clock noise on positioning performance.展开更多
In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is bu...In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.展开更多
Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers ...Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.展开更多
Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the ...Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.展开更多
Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is ...Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.展开更多
The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have hug...The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.展开更多
Semiconducting carbon nanotube (CNT) field effect transistor (FET) is attractive for constructing three-dimensional (3D) integrated circuits (ICs) because of its low-temperature processes and low power dissipation. Ho...Semiconducting carbon nanotube (CNT) field effect transistor (FET) is attractive for constructing three-dimensional (3D) integrated circuits (ICs) because of its low-temperature processes and low power dissipation. However, CNT based 3D ICs reported usually suffered from lower performance than that of monolayer CNT ICs. In this work, we develop a 3D IC technology through integrating multi-layer high performance CNT film FETs into one chip, and show that it promotes the operation speed of CNT based 3D ICs considerably. We also explore the advantage on ICs of 3D architecture, which brings 38% improvement on speed over two-dimensional (2D) one. Specially, we demonstrate the fabrication of 3D five-stage ring-oscillator circuits with an oscillation frequency of up to 680 MHz and stage delay of 0.15 ns, which represents the highest speed of 3D CNT-based ICs.展开更多
The development of an electrocatalyst based on abundant elements for the oxygen evolution reaction （OER） is important for water splitting associated with renewable energy sources. In this study, we develop an interc...The development of an electrocatalyst based on abundant elements for the oxygen evolution reaction （OER） is important for water splitting associated with renewable energy sources. In this study, we develop an interconnected Ni（Fe）OxHy nanosheet array on a stainless steel mesh （SSNNi） as an integrated OER electrode, without using any polymer binder. Benefiting from the well- defined three-dimensional （3D） architecture with highly exposed surface area, intimate contact between the active species and conductive substrate improved electron and mass transport capacity, facilitated electrolyte penetration, and improved mechanical stability. The SSNNi electrode also has excellent OER performance, including low overpotential, a small Tafel slope, and long-term durability in the alkaline electrolyte, making it one of the most promising OER electrodes developed.展开更多
Polymer insulating through-silicon-vias （TSVs） is an attractive approach for high-performance 3D integration systems. To further demonstrate the polymer insulating TSVs, this paper investigates the thermal stability...Polymer insulating through-silicon-vias （TSVs） is an attractive approach for high-performance 3D integration systems. To further demonstrate the polymer insulating TSVs, this paper investigates the thermal stability by measuring the leakage current under bias-temperature condition, studies the thermal stress characteristics with Finite Element Analysis （FEA）, and tries to improve the thermal mechanical reliability of high-density TSVs array by optimizing the geometry parameters of pitch, liner and redistribution layer （RDL）. The electrical measurements show the polymer insulating TSVs can maintain good insulation capability （less than 2x 10TM A） under challenging bias-temperature conditions of 20 V and 200~C, despite the leakage degra- dation observation. The FEA results show that the thermal stress is significantly reduced at the sidewall, but highly concen- trates at the surface, which is the potential location of mechanical failure. And, the analysis results indicate that the polymer insulating TSVs （diameter of 10 μm, depth of 50 μm） array with a pitch of 20 μm, liner thickness of 1 μm and RDL radius of 9 μm has an optimized thermal-mechanical reliability for application.展开更多
Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhance...Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhanced functionality.Inter-layer vias(ILVs),crucial components of M3D ICs,provide vertical connectivity between layers but are susceptible to manufacturing and operational defects,such as stuck-at faults(SAFs),shorts,and opens,which can compromise system reliability.These challenges necessitate advanced built-in self-test(BIST)methodologies to ensure robust fault detection and localization while minimizing the testing overhead.In this paper,we introduce a novel BIST architecture tailored to efficiently detect ILV defects,particularly in irregularly positioned ILVs,and approximately localize them within clusters,using a walking pattern approach.In the proposed BIST framework,ILVs are grouped according to the probability of fault occurrence,enabling efficient detection of all SAFs and bridging faults(BFs)and most multiple faults within each cluster.This strategy empowers designers to fine-tune fault coverage,localization precision,and test duration to meet specific design requirements.The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters.The method also enhances efficiency in terms of area and hardware utilization,particularly for larger circuit benchmarks.For instance,in the LU32PEENG benchmark,where ILVs are divided into 64 clusters,the power,area,and hardware overheads are minimized to 0.82%,1.03%,and 1.14%,respectively.展开更多
The rational design of electrodes is the key to achieving ultrahigh-power performance in electrochemical energy storage devices.Recently,we have constructed well-organized and integrated three-dimensional(3D)carbon tu...The rational design of electrodes is the key to achieving ultrahigh-power performance in electrochemical energy storage devices.Recently,we have constructed well-organized and integrated three-dimensional(3D)carbon tube(CT)grids(3D-CTGs)using a 3D porous anodic aluminum oxide template-assisted method as electrodes of electrical double-layer capacitors(EDLCs),showing excellent frequency response performance.The unique design warrants fast ion migration channels,excellent electronic conductivity,and good structural stability.This study achieved one of the highest carbon-based ultrahigh-power EDLCs with the 3D-CTG electrodes,resulting in ultrahigh power of 437 and 1708 W·cm−3 with aqueous and organic electrolytes,respectively.Capacitors constructed with these electrodes would have important application prospects in the ultrahigh-power output.The rational design and fabrication of the 3D-CTGs electrodes have demonstrated their capability to build capacitors with ultrahighpower performance and open up new possibilities for applications requiring high-power output.展开更多
Zn-air batteries(ZABs)as a potential energy conversion system suffer from low power density(typically≤200 mW·cm^(−2)).Recently,three-dimensional(3D)integrated air cathodes have demonstrated promising performance...Zn-air batteries(ZABs)as a potential energy conversion system suffer from low power density(typically≤200 mW·cm^(−2)).Recently,three-dimensional(3D)integrated air cathodes have demonstrated promising performance over traditional twodimensional(2D)plane ones,which is ascribed to enriched active sites and enhanced diffusion,but without experimental evidence.Herein,we applied a bubble pump consumption chronoamperometry(BPCC)method to quantitatively identify the gas diffusion coefficient(D)and effective catalytic sites density(ρEC)of the integrated air cathodes for ZABs.Furthermore,the D andρEC values can instruct consequent optimization on the growth of Co embedded N-doped carbon nanotubes(CoNCNTs)on carbon fiber paper(CFP)and aerophilicity tuning,giving 4 times D and 1.3 timesρEC over the conventional 2D Pt/C-CFP counterparts.As a result,using the CoNCNTs with half-wave potential of merely 0.78 V vs.RHE(Pt/C:0.89 V vs.RHE),the superaerophilic CoNCNTs-CFP cathode-based ZABs exhibited a superior peak power density of 245 mW·cm^(−2) over traditional 2D Pt/C-CFP counterparts,breaking the threshold of 200 mW·cm^(−2).This work reveals the intrinsic feature of the 3D integrated air cathodes by yielding exact D andρEC values,and demonstrates the feasibility of BPCC method for the optimization of integrated electrodes,bypassing trial-and-error strategy.展开更多
The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical ...The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.展开更多
Electrical contact materials are generally Ag-or Cu-based composites and play a critical role in ensuring the reliability and efficiency of electrical equipments and electronic instruments.The MAX(M is an early transi...Electrical contact materials are generally Ag-or Cu-based composites and play a critical role in ensuring the reliability and efficiency of electrical equipments and electronic instruments.The MAX(M is an early transition metal,A is an element from III or IV main groups,and X is carbon or/and nitrogen)phase ceramics display a unique combination of properties and may serve as an ideal reinforcement phase for electrical contact materials.The biological materials evolved in nature generally exhibit three-dimensional(3D)interpenetrating-phase architectures,which may offer useful inspiration for the architectural design of electrical contact materials.Here,a series of bi-continuous Ag-Ti_(3)SiC_(2) MAX phase composites with high ceramic contents exceeding 50 vol.%and having micron-and ultrafine-scaled 3D interpenetrating-phase architectures,wherein both constituents were continuous and mutually interspersed,were exploited by pressureless infiltration of Ag melt into partially sintered Ti_(3)SiC_(2) scaffolds.The mechanical and electrical properties as well as the friction and wear performance of the composites were investigated and revealed to be closely dependent on the ceramic contents and characteristic structural dimensions.The composites exhibited a good combination of properties with high hardness over 2.3 GPa,high flexural strength exceeding 530 MPa,decent fracture toughness over 10 MPa·m^(1/2),and good wear resistance with low wear rate at an order of 10^(-5)mm^(3)/(N·m),which were much superior compared to the counterparts made by powder metallurgy methods.In particular,the hardness,electrical conductivity,strength,and fracture toughness of the composites demonstrated a simultaneous improvement as the structure was refined from micron-to ultrafine-scales at equivalent ceramic contents.The good combination of properties along with the facile processing route makes the Ag-Ti_(3)SiC_(2)3D interpenetrating-phase composites appealing for electrical contact applications.展开更多
Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact eq...Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.展开更多
Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposer...Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposers,solder balls are placed next to the vias;however,this approach requires a large foot print for the input/output(I/O)connections.Therefore,in this study,we investigate the possibility of placing the solder balls directly on top of the vias,thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections.To reach this goal,inkjet printing(that is,piezo and super inkjet)was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer.The under bump metallization(UBM)pads were also successfully printed with inkjet technology on top of the polymer-filled vias,using either Ag or Au inks.The reliability of the TSV interposers was investigated by a temperature cycling stress test(−40℃ to+125℃).The stress test showed no impact on DC resistance of the TSVs;however,shrinkage and delamination of the polymer was observed,along with some micro-cracks in the UBM pads.For proof of concept,SnAgCu-based solder balls were jetted on the UBM pads.展开更多
This article reviews advanced process and electron device technology of integrated circuits,including recent featuring progress and potential solutions for future development.In 5 years,for pushing the performance of ...This article reviews advanced process and electron device technology of integrated circuits,including recent featuring progress and potential solutions for future development.In 5 years,for pushing the performance of fin field-effect transistors(FinFET)to its limitations,several processes and device boosters are provided.Then,the three-dimensional(3 D)integration schemes with alternative materials and device architectures will pave paths for future technology evolution.Finally,it could be concluded that Moore’s law will undoubtedly continue in the next 15 years.展开更多
文摘The space-air-ground integrated network(SAGIN)combines the superiority of the satellite,aerial,and ground communications,which is envisioned to provide high-precision positioning ability as well as seamless connectivity in the 5G and Beyond 5G(B5G)systems.In this paper,we propose a three-dimensional SAGIN localization scheme for ground agents utilizing multi-source information from satellites,base stations and unmanned aerial vehicles(UAVs).Based on the designed scheme,we derive the positioning performance bound and establish a distributed maximum likelihood algorithm to jointly estimate the positions and clock offsets of ground agents.Simulation results demonstrate the validity of the SAGIN localization scheme and reveal the effects of the number of satellites,the number of base stations,the number of UAVs and clock noise on positioning performance.
基金The National Natural Science Foundation of China(No.61674048,61574052,61474036,61371025)the Project of Anhui Institute of Economics and Management(No.YJKT1417T01)
文摘In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.
文摘Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.
基金fundings from the National Natural Science Foundation of China(Nos.62274013 and 92163206)the National Key Research and Development Program of China(No.2023YFB3405600)Science Fund for Creative Research Groups of the National Natural Science Foundation of China(No.12321004)。
文摘Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.
基金The Natural Science Foundation of Jiangsu Province(No.BK2012559)Qing Lan Project of Jiangsu Province
文摘Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.
基金the National Key R&D Program of China(Grant Nos.2018YFB0407501 and 2016YFA0201800)the National Natural Science Foundation of China(Grant Nos.61804173,61922083,61804167,61904200,and 61821091)the fourth China Association for Science and Technology Youth Talent Support Project(Grant No.2019QNRC001).
文摘The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.
基金supported by the National Key Research & Development Program (No.2016YFA0201901)the National Natural Science Foundation of China (Nos.61621061,61427901 and 61888102)the Beijing Municipal Science and Technology Commission (No.D171100006617002 1-2).
文摘Semiconducting carbon nanotube (CNT) field effect transistor (FET) is attractive for constructing three-dimensional (3D) integrated circuits (ICs) because of its low-temperature processes and low power dissipation. However, CNT based 3D ICs reported usually suffered from lower performance than that of monolayer CNT ICs. In this work, we develop a 3D IC technology through integrating multi-layer high performance CNT film FETs into one chip, and show that it promotes the operation speed of CNT based 3D ICs considerably. We also explore the advantage on ICs of 3D architecture, which brings 38% improvement on speed over two-dimensional (2D) one. Specially, we demonstrate the fabrication of 3D five-stage ring-oscillator circuits with an oscillation frequency of up to 680 MHz and stage delay of 0.15 ns, which represents the highest speed of 3D CNT-based ICs.
基金This work is financially supported by the National Natural Science Foundation of China （Nos. 51472209, U1401241, 51522101, 51471075, 5163100, and 51401084）, and Specialized Research Fund for the Doctoral Program of Higher Education of China （No. 20110061120040）.
文摘The development of an electrocatalyst based on abundant elements for the oxygen evolution reaction （OER） is important for water splitting associated with renewable energy sources. In this study, we develop an interconnected Ni（Fe）OxHy nanosheet array on a stainless steel mesh （SSNNi） as an integrated OER electrode, without using any polymer binder. Benefiting from the well- defined three-dimensional （3D） architecture with highly exposed surface area, intimate contact between the active species and conductive substrate improved electron and mass transport capacity, facilitated electrolyte penetration, and improved mechanical stability. The SSNNi electrode also has excellent OER performance, including low overpotential, a small Tafel slope, and long-term durability in the alkaline electrolyte, making it one of the most promising OER electrodes developed.
文摘Polymer insulating through-silicon-vias （TSVs） is an attractive approach for high-performance 3D integration systems. To further demonstrate the polymer insulating TSVs, this paper investigates the thermal stability by measuring the leakage current under bias-temperature condition, studies the thermal stress characteristics with Finite Element Analysis （FEA）, and tries to improve the thermal mechanical reliability of high-density TSVs array by optimizing the geometry parameters of pitch, liner and redistribution layer （RDL）. The electrical measurements show the polymer insulating TSVs can maintain good insulation capability （less than 2x 10TM A） under challenging bias-temperature conditions of 20 V and 200~C, despite the leakage degra- dation observation. The FEA results show that the thermal stress is significantly reduced at the sidewall, but highly concen- trates at the surface, which is the potential location of mechanical failure. And, the analysis results indicate that the polymer insulating TSVs （diameter of 10 μm, depth of 50 μm） array with a pitch of 20 μm, liner thickness of 1 μm and RDL radius of 9 μm has an optimized thermal-mechanical reliability for application.
文摘Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhanced functionality.Inter-layer vias(ILVs),crucial components of M3D ICs,provide vertical connectivity between layers but are susceptible to manufacturing and operational defects,such as stuck-at faults(SAFs),shorts,and opens,which can compromise system reliability.These challenges necessitate advanced built-in self-test(BIST)methodologies to ensure robust fault detection and localization while minimizing the testing overhead.In this paper,we introduce a novel BIST architecture tailored to efficiently detect ILV defects,particularly in irregularly positioned ILVs,and approximately localize them within clusters,using a walking pattern approach.In the proposed BIST framework,ILVs are grouped according to the probability of fault occurrence,enabling efficient detection of all SAFs and bridging faults(BFs)and most multiple faults within each cluster.This strategy empowers designers to fine-tune fault coverage,localization precision,and test duration to meet specific design requirements.The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters.The method also enhances efficiency in terms of area and hardware utilization,particularly for larger circuit benchmarks.For instance,in the LU32PEENG benchmark,where ILVs are divided into 64 clusters,the power,area,and hardware overheads are minimized to 0.82%,1.03%,and 1.14%,respectively.
基金supported by the National Natural Science Foundation of China(Nos.91963202,52072372,and 52232007).
文摘The rational design of electrodes is the key to achieving ultrahigh-power performance in electrochemical energy storage devices.Recently,we have constructed well-organized and integrated three-dimensional(3D)carbon tube(CT)grids(3D-CTGs)using a 3D porous anodic aluminum oxide template-assisted method as electrodes of electrical double-layer capacitors(EDLCs),showing excellent frequency response performance.The unique design warrants fast ion migration channels,excellent electronic conductivity,and good structural stability.This study achieved one of the highest carbon-based ultrahigh-power EDLCs with the 3D-CTG electrodes,resulting in ultrahigh power of 437 and 1708 W·cm−3 with aqueous and organic electrolytes,respectively.Capacitors constructed with these electrodes would have important application prospects in the ultrahigh-power output.The rational design and fabrication of the 3D-CTGs electrodes have demonstrated their capability to build capacitors with ultrahighpower performance and open up new possibilities for applications requiring high-power output.
基金supported by the National Natural Science Foundation of China(Nos.21935001 and 22379005)the Beijing Natural Science Foundation(No.Z210016)+3 种基金the National Key Research and Development Program of China(No.2018YFA0702002)Xinjiang Youth Science and Technology Top Talent Project(No.2022TSYCCX0053)Xinjiang Key Research and Development Project(No.2022B01003-2)the Fundamental Research Funds for the Central Universities,and the long-term subsidy mechanism from the Ministry of Finance and the Ministry of Education of PRC.
文摘Zn-air batteries(ZABs)as a potential energy conversion system suffer from low power density(typically≤200 mW·cm^(−2)).Recently,three-dimensional(3D)integrated air cathodes have demonstrated promising performance over traditional twodimensional(2D)plane ones,which is ascribed to enriched active sites and enhanced diffusion,but without experimental evidence.Herein,we applied a bubble pump consumption chronoamperometry(BPCC)method to quantitatively identify the gas diffusion coefficient(D)and effective catalytic sites density(ρEC)of the integrated air cathodes for ZABs.Furthermore,the D andρEC values can instruct consequent optimization on the growth of Co embedded N-doped carbon nanotubes(CoNCNTs)on carbon fiber paper(CFP)and aerophilicity tuning,giving 4 times D and 1.3 timesρEC over the conventional 2D Pt/C-CFP counterparts.As a result,using the CoNCNTs with half-wave potential of merely 0.78 V vs.RHE(Pt/C:0.89 V vs.RHE),the superaerophilic CoNCNTs-CFP cathode-based ZABs exhibited a superior peak power density of 245 mW·cm^(−2) over traditional 2D Pt/C-CFP counterparts,breaking the threshold of 200 mW·cm^(−2).This work reveals the intrinsic feature of the 3D integrated air cathodes by yielding exact D andρEC values,and demonstrates the feasibility of BPCC method for the optimization of integrated electrodes,bypassing trial-and-error strategy.
基金The work was partially funded by the Swedish Research Council,by the European 7^(th)Framework Programme under grant agreement FP7-NEMIAC(No.288670)by the European Research Council through the ERC Advanced Grant xMEMs(No.267528)and the ERC Starting Grant M&M’s(No.277879).
文摘The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.
基金supports from the National Key R&D Program of China(No.2020YFA0710404)the National Natural Science Foundation of China(No.52173269),the KC Wong Education Foundation(No.GJTD-2020-09)the Liaoning Revitalization Talents Program,and the Youth Innovation Promotion Association CAS(No.2019191).
文摘Electrical contact materials are generally Ag-or Cu-based composites and play a critical role in ensuring the reliability and efficiency of electrical equipments and electronic instruments.The MAX(M is an early transition metal,A is an element from III or IV main groups,and X is carbon or/and nitrogen)phase ceramics display a unique combination of properties and may serve as an ideal reinforcement phase for electrical contact materials.The biological materials evolved in nature generally exhibit three-dimensional(3D)interpenetrating-phase architectures,which may offer useful inspiration for the architectural design of electrical contact materials.Here,a series of bi-continuous Ag-Ti_(3)SiC_(2) MAX phase composites with high ceramic contents exceeding 50 vol.%and having micron-and ultrafine-scaled 3D interpenetrating-phase architectures,wherein both constituents were continuous and mutually interspersed,were exploited by pressureless infiltration of Ag melt into partially sintered Ti_(3)SiC_(2) scaffolds.The mechanical and electrical properties as well as the friction and wear performance of the composites were investigated and revealed to be closely dependent on the ceramic contents and characteristic structural dimensions.The composites exhibited a good combination of properties with high hardness over 2.3 GPa,high flexural strength exceeding 530 MPa,decent fracture toughness over 10 MPa·m^(1/2),and good wear resistance with low wear rate at an order of 10^(-5)mm^(3)/(N·m),which were much superior compared to the counterparts made by powder metallurgy methods.In particular,the hardness,electrical conductivity,strength,and fracture toughness of the composites demonstrated a simultaneous improvement as the structure was refined from micron-to ultrafine-scales at equivalent ceramic contents.The good combination of properties along with the facile processing route makes the Ag-Ti_(3)SiC_(2)3D interpenetrating-phase composites appealing for electrical contact applications.
基金supported by the National Natural Science Foundation of China(Nos.61234002,61006028,61204044)the National High-Tech Program of China(Nos.2012AA012302,2013AA011203)
文摘Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.
基金This work is supported by ENIAC-JU Project Prominent Grant No 324189 and Tekes Grant No.40336/12 and Vinnova Grants Nos.2012-04301,2012-04287,and 2012-04314MM is supported by the Academy of Finland Grant Nos.288945 and 294119The work of Silex and KTH was funded in part through an Industrial Ph.D.grant from the Swedish Foundation for Strategic Research(SSF),Grant No.ID14-0033.
文摘Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposers,solder balls are placed next to the vias;however,this approach requires a large foot print for the input/output(I/O)connections.Therefore,in this study,we investigate the possibility of placing the solder balls directly on top of the vias,thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections.To reach this goal,inkjet printing(that is,piezo and super inkjet)was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer.The under bump metallization(UBM)pads were also successfully printed with inkjet technology on top of the polymer-filled vias,using either Ag or Au inks.The reliability of the TSV interposers was investigated by a temperature cycling stress test(−40℃ to+125℃).The stress test showed no impact on DC resistance of the TSVs;however,shrinkage and delamination of the polymer was observed,along with some micro-cracks in the UBM pads.For proof of concept,SnAgCu-based solder balls were jetted on the UBM pads.
基金the support from the members of Integrated Circuit Advanced Process R&D Center,Institute of Microelectronics,Chinese Academy of Sciencessupported in part by the National Key Project of Science and Technology of China(No.2017ZX02315001-002)。
文摘This article reviews advanced process and electron device technology of integrated circuits,including recent featuring progress and potential solutions for future development.In 5 years,for pushing the performance of fin field-effect transistors(FinFET)to its limitations,several processes and device boosters are provided.Then,the three-dimensional(3 D)integration schemes with alternative materials and device architectures will pave paths for future technology evolution.Finally,it could be concluded that Moore’s law will undoubtedly continue in the next 15 years.
