A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,...A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks （CLBs） in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip （SoC） hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.展开更多
Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre...Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre- quency-directed run-length （AFDR） codes. Different [rom frequency-directed run-length （FDR） codes, AFDR encodes both 0- and 1-runs and uses the same codes to the equal length runs. It also modifies the codes for 00 and 11 to improve the compression performance. Experimental results for ISCAS 89 benchmark circuits show that AFDR codes achieve higher compression ratio than FDR and other compression codes.展开更多
This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratio...This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.展开更多
基金supported by the Key Techniques of FPGA Architecture under Grant No. 9140A08010106QT9201
文摘A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks （CLBs） in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip （SoC） hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
基金Supported by the National Natural Science Foundation of China(61076019,61106018)the Aeronautical Science Foundation of China(20115552031)+3 种基金the China Postdoctoral Science Foundation(20100481134)the Jiangsu Province Key Technology R&D Program(BE2010003)the Nanjing University of Aeronautics and Astronautics Research Funding(NS2010115)the Nanjing University of Aeronatics and Astronautics Initial Funding for Talented Faculty(1004-YAH10027)~~
文摘Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre- quency-directed run-length （AFDR） codes. Different [rom frequency-directed run-length （FDR） codes, AFDR encodes both 0- and 1-runs and uses the same codes to the equal length runs. It also modifies the codes for 00 and 11 to improve the compression performance. Experimental results for ISCAS 89 benchmark circuits show that AFDR codes achieve higher compression ratio than FDR and other compression codes.
基金国家自然科学基金，the Sci. & Technol. Project of Beijing，中国科学院资助项目，Synopsys公司资助项目
文摘This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.
