A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperatu...A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak inversion. The proposed circuit, designed with a 0.6 Izm standard CMOS technology, gives a good temperature coefficient of 31ppm/℃ [-50-100℃] at a 1.8V supply, and also achieves line regulation of 0.01%/V and-120dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and Line regulation.展开更多
comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled fro...comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit＇s performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature （from room temperature down to 77 K） operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity （DNL） and 0.59 LSB maximum integral nonlinearity （1NL）. It achieves 9.3 bit effective number of bits （ENOB） with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm^2.展开更多
To design a high-precision reference, the various error sources have been analyzed and compensated with a compact 111 mV resistor-trim scheme and the upper and lower extremes of the reference precision are also temper...To design a high-precision reference, the various error sources have been analyzed and compensated with a compact 111 mV resistor-trim scheme and the upper and lower extremes of the reference precision are also temperature-compensated. At room temperature, the yield of ：50.5% precision is 96% and ：50.2% is 78%.展开更多
文摘A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak inversion. The proposed circuit, designed with a 0.6 Izm standard CMOS technology, gives a good temperature coefficient of 31ppm/℃ [-50-100℃] at a 1.8V supply, and also achieves line regulation of 0.01%/V and-120dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and Line regulation.
文摘comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit＇s performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature （from room temperature down to 77 K） operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity （DNL） and 0.59 LSB maximum integral nonlinearity （1NL）. It achieves 9.3 bit effective number of bits （ENOB） with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm^2.
基金supported by the National Natural Science Foundation of China(Nos.61366006,No.51261015)the Natural Science Foundation of Gansu(No.1308RJZA238)
文摘To design a high-precision reference, the various error sources have been analyzed and compensated with a compact 111 mV resistor-trim scheme and the upper and lower extremes of the reference precision are also temperature-compensated. At room temperature, the yield of ：50.5% precision is 96% and ：50.2% is 78%.
