The tail bits of intermediate resistance states（IRSs） achieved in the SET process（IRSS） and the RESET process（IRSR） of conductive-bridge random-access memory were investigated. Two types of tail bits were observ...The tail bits of intermediate resistance states（IRSs） achieved in the SET process（IRSS） and the RESET process（IRSR） of conductive-bridge random-access memory were investigated. Two types of tail bits were observed, depending on the filament morphology after the SET/RESET operation.（i） Tail bits resulting from lateral diffusion of Cu ions introduced an abrupt increase of device resistance from IRS to ultrahigh-resistance state, which mainly happened in IRSS.（ii） Tail bits induced by the vertical diffusion of Cu ions showed a gradual shift of resistance toward lower value. Statistical results show that more than 95% of tail bits are generated in IRSS. To achieve a reliable IRS for multilevel cell（MLC） operation, it is desirable to program the IRS in RESET operation. The mechanism of tail bit generation that is disclosed here provides a clear guideline for the data retention optimization of MLC resistive random-access memory cells.展开更多
基金Project supported by the Ministry of Science and Technology of China(Grant Nos.2016YFA0203800,2016YFA0201803,and 2018YFB0407502)the National Natural Science Foundation of China(Grant Nos.61522408,61334007,and 61521064)+1 种基金Beijing Municipal Science&Technology Commission Program,China(Grant No.Z161100000216153)Huawei Data Center Technology Laboratory
文摘The tail bits of intermediate resistance states（IRSs） achieved in the SET process（IRSS） and the RESET process（IRSR） of conductive-bridge random-access memory were investigated. Two types of tail bits were observed, depending on the filament morphology after the SET/RESET operation.（i） Tail bits resulting from lateral diffusion of Cu ions introduced an abrupt increase of device resistance from IRS to ultrahigh-resistance state, which mainly happened in IRSS.（ii） Tail bits induced by the vertical diffusion of Cu ions showed a gradual shift of resistance toward lower value. Statistical results show that more than 95% of tail bits are generated in IRSS. To achieve a reliable IRS for multilevel cell（MLC） operation, it is desirable to program the IRS in RESET operation. The mechanism of tail bit generation that is disclosed here provides a clear guideline for the data retention optimization of MLC resistive random-access memory cells.
