In order to get rid of the dependence on high-precision centrifuges in accelerometer nonlinear coefficients calibration,this paper proposes a system-level calibration method for field condition.Firstly,a 42-dimension ...In order to get rid of the dependence on high-precision centrifuges in accelerometer nonlinear coefficients calibration,this paper proposes a system-level calibration method for field condition.Firstly,a 42-dimension Kalman filter is constructed to reduce impact brought by turntable.Then,a biaxial rotation path is designed based on the accelerometer output model,including orthogonal 22 positions and tilt 12 positions,which enhances gravity excitation on nonlinear coefficients of accelerometer.Finally,sampling is carried out for calibration and further experiments.The results of static inertial navigation experiments lasting 4000 s show that compared with the traditional method,the proposed method reduces the position error by about 390 m.展开更多
This paper presents two approaches for system-level simulation of force-balance accelerometers. The derivation of the system-level model is elaborated and simulation results are obtained from the implementation of tho...This paper presents two approaches for system-level simulation of force-balance accelerometers. The derivation of the system-level model is elaborated and simulation results are obtained from the implementation of those strategies on the fabricated silicon force-balance MEMS accelerometer. The mathematical model presented is implemented in VHDL- AMS and SIMULINK TM,respectively. The simulation results from the two approaches are compared and show a slight difference. Using VHDL-AMS is flexible,reusable,and more accurate. But there is not a mature solver developed for the language and this approach takes more time, while the simulation model can be easily built and quickly evaluated using SIMULINK.展开更多
In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity o...In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.展开更多
In this paper we propose an equation model of system-level fault diagnoses, and construct corresponding theory and algorithms. People can turn any PMC model on ex-test into an equivalent equation (or a system of equat...In this paper we propose an equation model of system-level fault diagnoses, and construct corresponding theory and algorithms. People can turn any PMC model on ex-test into an equivalent equation (or a system of equations), and find all consistent fault patterns based on the equation model. We can also find all fault patterns, in which the fault node numbers are less than or equal to t without supposing t-diagnosable. It is not impossible for all graphic models.展开更多
With the development of EMC technology, EMC assessment has become increasingly important in EMC design. Although numerous EMC assessment models are available today, few of them can provide a tradeoff between efficienc...With the development of EMC technology, EMC assessment has become increasingly important in EMC design. Although numerous EMC assessment models are available today, few of them can provide a tradeoff between efficiency and accuracy for the specific case of military vehicular communication systems. Face to this situation, a modified four-level assessment model is proposed in the paper. First, the development of EMC assessment technology is briefly reviewed, and the theoretical mechanism of EMI environment is introduced. Then, the architecture of the proposed model is outlined, and the assessment methods are explored. To demonstrate the application of it, an example involving a communication system in a military vehicle is presented. From the physical layer to the signal layer, a hierarchical assessment on the entire system is successfully performed based on the proposed model, and we can make a qualitative EMC assessment on the EMC performance of the system. Based on a comparison with the traditional model, we conclude that the proposed model is more accurate, more efficient and less time-consuming, which is suitable for the EMC assessment on militaryvehicular communication systems. We hope that the proposed model will serve as a useful reference for system-level EMC assessments for other systems.展开更多
---Double data rate synchronous dynamic random access memory （DDR3） has become one of the most mainstream applications in current server and computer systems. In order to quickly set up a system-level signal integri...---Double data rate synchronous dynamic random access memory （DDR3） has become one of the most mainstream applications in current server and computer systems. In order to quickly set up a system-level signal integrity （SI） simulation flow for the DDR3 interface, two system-level SI simulation methodologies, which are board-level S-parameter extraction in the frequency-domain and system-level simulation assumptions in the time domain, are introduced in this paper. By comparing the flow of Speed2000 and PowerSI/Hspice, PowerSI is chosen for the printed circuit board （PCB） board-level S-parameter extraction, while Tektronix oscilloscope （TDS7404） is used for the DDR3 waveform measurement. The lab measurement shows good agreement between simulation and measurement. The study shows that the combination of PowerSI and Hspice is recommended for quick system-level DDR3 SI simulation.展开更多
Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the...Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the abstraction level is nowadays widely seen as a solution to bridge the gap between the increasing system complexity and the low design productivity. For this, several system-level design tools and methodologies have been introduced to efficiently explore the design space of heterogeneous signal processing systems. In this paper, we demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient peformance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems. For this purpose, we have selected a system level design of a very high complexity media application;a H.264/AVC (Advanced Video Codec) video encoder. The encoding performances will be evaluated using system-level simulations targeting multiple heterogeneous multiprocessors platforms.展开更多
基金supported by the National Natural Science Foundation of China(42276199).
文摘In order to get rid of the dependence on high-precision centrifuges in accelerometer nonlinear coefficients calibration,this paper proposes a system-level calibration method for field condition.Firstly,a 42-dimension Kalman filter is constructed to reduce impact brought by turntable.Then,a biaxial rotation path is designed based on the accelerometer output model,including orthogonal 22 positions and tilt 12 positions,which enhances gravity excitation on nonlinear coefficients of accelerometer.Finally,sampling is carried out for calibration and further experiments.The results of static inertial navigation experiments lasting 4000 s show that compared with the traditional method,the proposed method reduces the position error by about 390 m.
文摘This paper presents two approaches for system-level simulation of force-balance accelerometers. The derivation of the system-level model is elaborated and simulation results are obtained from the implementation of those strategies on the fabricated silicon force-balance MEMS accelerometer. The mathematical model presented is implemented in VHDL- AMS and SIMULINK TM,respectively. The simulation results from the two approaches are compared and show a slight difference. Using VHDL-AMS is flexible,reusable,and more accurate. But there is not a mature solver developed for the language and this approach takes more time, while the simulation model can be easily built and quickly evaluated using SIMULINK.
基金supported by the National High Technology Research and Development Program of China (863 Program) (2002AA1Z1490)Specialized Research Fund for the Doctoral Program of Higher Education (20040486049)the University Cooperative Research Fund of Huawei Technology Co., Ltd
文摘In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.
基金Project supported by the National Natural Science Foundation of China! (No.69973016).
文摘In this paper we propose an equation model of system-level fault diagnoses, and construct corresponding theory and algorithms. People can turn any PMC model on ex-test into an equivalent equation (or a system of equations), and find all consistent fault patterns based on the equation model. We can also find all fault patterns, in which the fault node numbers are less than or equal to t without supposing t-diagnosable. It is not impossible for all graphic models.
基金supported by the National Moon Exploration Program of China (No. TY3Q20110020)in part supported by the 13th Five-Year Community Technology Research Program of National Equipment Development Department of China (No.41409020301)the National Natural Science Foundation of China (50971094)
文摘With the development of EMC technology, EMC assessment has become increasingly important in EMC design. Although numerous EMC assessment models are available today, few of them can provide a tradeoff between efficiency and accuracy for the specific case of military vehicular communication systems. Face to this situation, a modified four-level assessment model is proposed in the paper. First, the development of EMC assessment technology is briefly reviewed, and the theoretical mechanism of EMI environment is introduced. Then, the architecture of the proposed model is outlined, and the assessment methods are explored. To demonstrate the application of it, an example involving a communication system in a military vehicle is presented. From the physical layer to the signal layer, a hierarchical assessment on the entire system is successfully performed based on the proposed model, and we can make a qualitative EMC assessment on the EMC performance of the system. Based on a comparison with the traditional model, we conclude that the proposed model is more accurate, more efficient and less time-consuming, which is suitable for the EMC assessment on militaryvehicular communication systems. We hope that the proposed model will serve as a useful reference for system-level EMC assessments for other systems.
基金supported by the National Natural Science Foundation of China under Grant No.61161001
文摘---Double data rate synchronous dynamic random access memory （DDR3） has become one of the most mainstream applications in current server and computer systems. In order to quickly set up a system-level signal integrity （SI） simulation flow for the DDR3 interface, two system-level SI simulation methodologies, which are board-level S-parameter extraction in the frequency-domain and system-level simulation assumptions in the time domain, are introduced in this paper. By comparing the flow of Speed2000 and PowerSI/Hspice, PowerSI is chosen for the printed circuit board （PCB） board-level S-parameter extraction, while Tektronix oscilloscope （TDS7404） is used for the DDR3 waveform measurement. The lab measurement shows good agreement between simulation and measurement. The study shows that the combination of PowerSI and Hspice is recommended for quick system-level DDR3 SI simulation.
文摘Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the abstraction level is nowadays widely seen as a solution to bridge the gap between the increasing system complexity and the low design productivity. For this, several system-level design tools and methodologies have been introduced to efficiently explore the design space of heterogeneous signal processing systems. In this paper, we demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient peformance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems. For this purpose, we have selected a system level design of a very high complexity media application;a H.264/AVC (Advanced Video Codec) video encoder. The encoding performances will be evaluated using system-level simulations targeting multiple heterogeneous multiprocessors platforms.
