Ribosomally synthesized and post-translationally modified peptides(RiPPs)constitute a vast and diverse family of bioactive peptides.These peptides,synthesized by ribosomes and subsequently modified by various tailorin...Ribosomally synthesized and post-translationally modified peptides(RiPPs)constitute a vast and diverse family of bioactive peptides.These peptides,synthesized by ribosomes and subsequently modified by various tailoring enzymes,possess a wide chemical space.Among these modifications,radical S-adenosylmethionine(rSAM)enzymes employ unique radical chemistry to introduce a variety of novel peptide structures,which are crucial for their activity.This review examines the major types of modifications in RiPPs catalyzed by rSAM enzymes,incorporating recent advancements in protein structure analysis techniques and computational methods.Additionally,it elucidates the diverse catalytic mechanisms and substrate selectivity of these enzymes through an analysis of the latest crystal structures.展开更多
In this study,we demonstrate the direct in-situ synthesis of NiTi alloys with tunable chemical com-position(Ni/Ti atomic ratio)and corresponding thermomechanical response.This synthesis is achieved by regulating the f...In this study,we demonstrate the direct in-situ synthesis of NiTi alloys with tunable chemical com-position(Ni/Ti atomic ratio)and corresponding thermomechanical response.This synthesis is achieved by regulating the feeding speed ratio of pure Ni and Ti wires during the additive manufacturing pro-cess based on dual-wire-feed electron beam directed energy deposition(EB-DED)technology.Under ap-propriate process conditions,the resulting NiTi alloys exhibit a controllable evolution around the near-equiatomic composition and display a typical columnar grain morphology characteristic of additively manufactured NiTi alloys.With an increase in Ni content(shifting from Ti-rich to Ni-rich),the second phase particles present in the samples change from Ti-rich phase(Ti_(2) Ni)to Ni-rich phases(such as Ni4 Ti3 and Ni3 Ti_(2)).The phase transformation temperatures gradually decrease with increasing Ni content,and the predominant matrix phase transitions from martensite to austenite.The as-built NiTi alloy exhibits a typical tensile curve with a good tensile elongation of 11%,fabricated under suitable composition and microstructure conditions.This result surpasses values reported in current in-situ synthesized NiTi alloys through additive manufacturing methods.Moreover,it almost reaches the levels achieved by additively manufactured NiTi alloys using pre-alloyed raw materials.Furthermore,this study reports,for the first time in the field of in-situ synthesized NiTi alloys,a good tensile shape memory effect,achieving an im-pressive recovery rate of up to 70%under a tensile strain of 6%.This investigation provides a meaningful theoretical perspective and technical strategy for the integrated customization of NiTi alloy components in structure,composition,and function.This low-cost and high-efficiency approach is particularly attrac-tive for the preparation of functional graded,large-scale and disposable NiTi components.展开更多
针对具有多维状态变量、多种工作模式和故障模式的复杂工程系统,提出一种基于综合健康指数(synthesized health index,SHI)与相关向量机(relevance vector machine,RVM)的系统级失效预测方法。在离线训练阶段,先根据有限失效历史数据建...针对具有多维状态变量、多种工作模式和故障模式的复杂工程系统,提出一种基于综合健康指数(synthesized health index,SHI)与相关向量机(relevance vector machine,RVM)的系统级失效预测方法。在离线训练阶段,先根据有限失效历史数据建立各工作模式下的健康评估模型,并据此获得各历史退化轨迹的SHI序列;然后再使用RVM对这些序列进行回归处理,进而辨识出与回归曲线最为匹配的函数模型。在线预测阶段,先运用健康评估模型计算当前设备的SHI序列并进行RVM回归,再拟合出离线阶段确定的函数模型并添加时变噪声;最后,外推预测出系统剩余使用寿命的概率密度分布。该方法成功应用到涡轮发动机的失效预测案例。展开更多
An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods ...An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.展开更多
A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 presc...A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.展开更多
A complete closed-loop third order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between th...A complete closed-loop third order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between the process,voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed. A variation margin is proposed for stability compensation. Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total variation. A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods.展开更多
A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator ...A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.展开更多
A new FM transmitter is reported. It adopts a fractional-N PLL synthesizer to realize the FM modulator. An extra offset current has also been applied to eliminate the effects of the mismatch in CP. The chip is fabrica...A new FM transmitter is reported. It adopts a fractional-N PLL synthesizer to realize the FM modulator. An extra offset current has also been applied to eliminate the effects of the mismatch in CP. The chip is fabricated with CSMC 0.5μm DPTM CMOS technology. Experiments show that it achieves THD≤0.08% and SNR≤ 82dB,and the maximum outband emission energy ≤ 90dBc/Hz. Furthermore,it also uses an auto frequency adjusting method to avoid tuning up the external inductances. All these merits are very suitable for FM transmission.展开更多
By analyzing hundreds of capillary pressure curves, the controlling factors of shape and type of capillary pressure curves are found and a novel method is presented to construct capillary pressure curves by using rese...By analyzing hundreds of capillary pressure curves, the controlling factors of shape and type of capillary pressure curves are found and a novel method is presented to construct capillary pressure curves by using reservoir permeability and a synthesized index. The accuracy of this new method is verified by mercury-injection experiments. Considering the limited quantity of capillary pressure data, a new method is developed to extract the Swanson parameter from the NMR T2 distribution and estimate reservoir permeability. Integrating with NMR total porosity, reservoir capillary pressure curves can be constructed to evaluate reservoir pore structure in the intervals with NMR log data. An in-situ example of evaluating reservoir pore structure using the capillary pressure curves by this new method is presented. The result shows that it accurately detects the change in reservoir pore structure as a function of depth.展开更多
Sol-gel method is a technique to synthesize inorganic materials based on wet-chemical reaction theory. The results have shown that reactants tetraethyl orthosilicate （TEOS） and Ca（NO3）2·4H2O can form sol and ...Sol-gel method is a technique to synthesize inorganic materials based on wet-chemical reaction theory. The results have shown that reactants tetraethyl orthosilicate （TEOS） and Ca（NO3）2·4H2O can form sol and gel in solution at 50-60 ℃, and the cosolvents are propyl alcohol （NPA） and H2O, the catalyst is HNO3. This sol-gel is burned for 12 hat 1 350-1 450 ℃ so that the organic matter, free water （moisture） in sol-gel system are removed and a solid reaction has taken place to form the resulting product. The product has been confirmed to be C3S by XRD, SEM and 29Si MAS NMR, as well as free lime content of the product which is less than 0.2% was determined by propanetriol-ethanol-method. The analysis determined by EDXA has indicated that the n（Ca）/n（Si） ratio in corresponding to micro-region is close to theoretical value of 3∶1. This resulting product is C3S with Si sites of Q0 polymerization, and has higher purity and hydraulic activities at earlier age of hydration.展开更多
A series of （4-（2,4,5-trifluorophenyl）piperazin-1-yl） methanone derivatives 9a–k as potential dipeptidyl peptidase-4 （DPP-4） inhibitors were synthesized by microwave assisted nucleophilic substitution of 1,2,4,...A series of （4-（2,4,5-trifluorophenyl）piperazin-1-yl） methanone derivatives 9a–k as potential dipeptidyl peptidase-4 （DPP-4） inhibitors were synthesized by microwave assisted nucleophilic substitution of 1,2,4,5-tetrafluorobenzene with piperazine, followed by carbamoylation and condensation. The inhibitory activities of these new compounds on DPP-4 were evaluated in vitro, and compounds 9d and 9g showed moderate inhibitory activities.展开更多
Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is p...Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.展开更多
A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused o...A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.展开更多
This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation ...This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.展开更多
An ＂automatic power down＂ method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode. Implemented with the TSMC 0.25vm mi...An ＂automatic power down＂ method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode. Implemented with the TSMC 0.25vm mixed-sig- nal CMOS process,the 4/5 MOS current mode logic prescaler is designed with this automatic power down technique. The simulation results show that the new 4/5 prescaler is immune to the ＂wake-up＂ issue and thereby retains the same maxi- mum operating frequency as the conventional prescaler. An integer-N divider with this proposed prescaler and with the di- vision ratio 66/67 is manufactured,and it is estimated to save more than 20% of the power compared with the conventional 4/5 prescaler.展开更多
The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communi...The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.展开更多
The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to...The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.展开更多
基金supported by the National Key Research and Development Program of China(No.2023YFA0916000)the National Natural Science Foundation of China(No.32371324)the High-level Talent Startup Fund provided by China Pharmaceutical University.
文摘Ribosomally synthesized and post-translationally modified peptides(RiPPs)constitute a vast and diverse family of bioactive peptides.These peptides,synthesized by ribosomes and subsequently modified by various tailoring enzymes,possess a wide chemical space.Among these modifications,radical S-adenosylmethionine(rSAM)enzymes employ unique radical chemistry to introduce a variety of novel peptide structures,which are crucial for their activity.This review examines the major types of modifications in RiPPs catalyzed by rSAM enzymes,incorporating recent advancements in protein structure analysis techniques and computational methods.Additionally,it elucidates the diverse catalytic mechanisms and substrate selectivity of these enzymes through an analysis of the latest crystal structures.
基金the State Key Laboratory of Tribology in Advanced Equipment(Project code:SKLT2022C20)Postdoc Matching Fund Scheme of The Hong Kong Polytechnic University(Project code:1-W283)+3 种基金Research Institute of Advanced Manufacturing at The Hong Kong Polytechnic University(PolyU)(Project code:CD9E,CD8Y)PolyU Research and Inno-vation Office(Project code:BBR5)Departmental General Research Fund of the Department of Industrial and Systems Engineering of The Hong Kong Polytechnic University(Project code:G-UAKX)the funding support for the State Key Laboratories in Hong Kong from the Innovation and Technology Commission of the Govern-ment of the Hong Kong Special Administrative Region,China.
文摘In this study,we demonstrate the direct in-situ synthesis of NiTi alloys with tunable chemical com-position(Ni/Ti atomic ratio)and corresponding thermomechanical response.This synthesis is achieved by regulating the feeding speed ratio of pure Ni and Ti wires during the additive manufacturing pro-cess based on dual-wire-feed electron beam directed energy deposition(EB-DED)technology.Under ap-propriate process conditions,the resulting NiTi alloys exhibit a controllable evolution around the near-equiatomic composition and display a typical columnar grain morphology characteristic of additively manufactured NiTi alloys.With an increase in Ni content(shifting from Ti-rich to Ni-rich),the second phase particles present in the samples change from Ti-rich phase(Ti_(2) Ni)to Ni-rich phases(such as Ni4 Ti3 and Ni3 Ti_(2)).The phase transformation temperatures gradually decrease with increasing Ni content,and the predominant matrix phase transitions from martensite to austenite.The as-built NiTi alloy exhibits a typical tensile curve with a good tensile elongation of 11%,fabricated under suitable composition and microstructure conditions.This result surpasses values reported in current in-situ synthesized NiTi alloys through additive manufacturing methods.Moreover,it almost reaches the levels achieved by additively manufactured NiTi alloys using pre-alloyed raw materials.Furthermore,this study reports,for the first time in the field of in-situ synthesized NiTi alloys,a good tensile shape memory effect,achieving an im-pressive recovery rate of up to 70%under a tensile strain of 6%.This investigation provides a meaningful theoretical perspective and technical strategy for the integrated customization of NiTi alloy components in structure,composition,and function.This low-cost and high-efficiency approach is particularly attrac-tive for the preparation of functional graded,large-scale and disposable NiTi components.
文摘针对具有多维状态变量、多种工作模式和故障模式的复杂工程系统,提出一种基于综合健康指数(synthesized health index,SHI)与相关向量机(relevance vector machine,RVM)的系统级失效预测方法。在离线训练阶段,先根据有限失效历史数据建立各工作模式下的健康评估模型,并据此获得各历史退化轨迹的SHI序列;然后再使用RVM对这些序列进行回归处理,进而辨识出与回归曲线最为匹配的函数模型。在线预测阶段,先运用健康评估模型计算当前设备的SHI序列并进行RVM回归,再拟合出离线阶段确定的函数模型并添加时变噪声;最后,外推预测出系统剩余使用寿命的概率密度分布。该方法成功应用到涡轮发动机的失效预测案例。
文摘An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.
文摘A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.
文摘A complete closed-loop third order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between the process,voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed. A variation margin is proposed for stability compensation. Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total variation. A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods.
文摘A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.
文摘A new FM transmitter is reported. It adopts a fractional-N PLL synthesizer to realize the FM modulator. An extra offset current has also been applied to eliminate the effects of the mismatch in CP. The chip is fabricated with CSMC 0.5μm DPTM CMOS technology. Experiments show that it achieves THD≤0.08% and SNR≤ 82dB,and the maximum outband emission energy ≤ 90dBc/Hz. Furthermore,it also uses an auto frequency adjusting method to avoid tuning up the external inductances. All these merits are very suitable for FM transmission.
文摘By analyzing hundreds of capillary pressure curves, the controlling factors of shape and type of capillary pressure curves are found and a novel method is presented to construct capillary pressure curves by using reservoir permeability and a synthesized index. The accuracy of this new method is verified by mercury-injection experiments. Considering the limited quantity of capillary pressure data, a new method is developed to extract the Swanson parameter from the NMR T2 distribution and estimate reservoir permeability. Integrating with NMR total porosity, reservoir capillary pressure curves can be constructed to evaluate reservoir pore structure in the intervals with NMR log data. An in-situ example of evaluating reservoir pore structure using the capillary pressure curves by this new method is presented. The result shows that it accurately detects the change in reservoir pore structure as a function of depth.
基金Financially supported by National Basic Research Program of China (973Program)(No. 2009CB623200)National Natural Science Foundation of China(No.50972109)Doctoral Program of Higher Education (No. 20090141110021)
文摘Sol-gel method is a technique to synthesize inorganic materials based on wet-chemical reaction theory. The results have shown that reactants tetraethyl orthosilicate （TEOS） and Ca（NO3）2·4H2O can form sol and gel in solution at 50-60 ℃, and the cosolvents are propyl alcohol （NPA） and H2O, the catalyst is HNO3. This sol-gel is burned for 12 hat 1 350-1 450 ℃ so that the organic matter, free water （moisture） in sol-gel system are removed and a solid reaction has taken place to form the resulting product. The product has been confirmed to be C3S by XRD, SEM and 29Si MAS NMR, as well as free lime content of the product which is less than 0.2% was determined by propanetriol-ethanol-method. The analysis determined by EDXA has indicated that the n（Ca）/n（Si） ratio in corresponding to micro-region is close to theoretical value of 3∶1. This resulting product is C3S with Si sites of Q0 polymerization, and has higher purity and hydraulic activities at earlier age of hydration.
基金supported by Nationa l973 Projects from the Ministry of Science and Technology of China(Grant No.2010CB735601 and 2012CB724501)
文摘A series of （4-（2,4,5-trifluorophenyl）piperazin-1-yl） methanone derivatives 9a–k as potential dipeptidyl peptidase-4 （DPP-4） inhibitors were synthesized by microwave assisted nucleophilic substitution of 1,2,4,5-tetrafluorobenzene with piperazine, followed by carbamoylation and condensation. The inhibitory activities of these new compounds on DPP-4 were evaluated in vitro, and compounds 9d and 9g showed moderate inhibitory activities.
文摘Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.
文摘A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.
基金The Research Project of Science and Technology at the University of Inner Mongolia Autonomous Region(No.NJZY11016)the Innovation Fund of the Ministry of Science and Technology for Small and Medium Sized Enterprises of China(No.11C26213211234)
文摘This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.
文摘An ＂automatic power down＂ method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode. Implemented with the TSMC 0.25vm mixed-sig- nal CMOS process,the 4/5 MOS current mode logic prescaler is designed with this automatic power down technique. The simulation results show that the new 4/5 prescaler is immune to the ＂wake-up＂ issue and thereby retains the same maxi- mum operating frequency as the conventional prescaler. An integer-N divider with this proposed prescaler and with the di- vision ratio 66/67 is manufactured,and it is estimated to save more than 20% of the power compared with the conventional 4/5 prescaler.
基金The National Natural Science Foundation of China(No.60472057)
文摘The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.
文摘The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.
