Objective:To examine and compare the synchronization of different brain regions during the Chinese and English Stroop tasks.Methods.Ten native Chinese speakers with a moderate command of English participated in this s...Objective:To examine and compare the synchronization of different brain regions during the Chinese and English Stroop tasks.Methods.Ten native Chinese speakers with a moderate command of English participated in this study,and event-related potentials were recorded while participants performed the Stroop task.Then wavelet-based estimation of instantaneous EEG coherence was applied to investigate the synchronization of different brain regions during Stroop task.Results:A greater negativity for the in- congruent situation than congruent situation appeared from 350ms to 600ms post-stimulus onset over frontal,central,and parietal regions in Chinese Stroop task,while the negativity was absent in English Stroop task.However,not only in Chinese Stroop task but also in English Stroop task was it found signif- icantly higher EEG coherences for the incongruent situation than congruent situation over frontal,pari- etal,and frontoparietal regions before 400ms post stimulus onset atβ(13-30 Hz) frequency band.Conclu- sion:This finding indicated that wavelet-based coherence is more exquisite tool to analyze brain electro- physiological signals associated with complex cognitive task than ERP component,and that functional syn- chronization indexed by EEG coherence is enhanced at the earlier stage while processing the conflicting in- formation for the incongruent stimulus.展开更多
SIGNAL belongs to the synchronous languages family which are widely used in the design of safety-critical real-time systems such as avionics, space systems, and nu- clear power plants. This paper reports a compiler pr...SIGNAL belongs to the synchronous languages family which are widely used in the design of safety-critical real-time systems such as avionics, space systems, and nu- clear power plants. This paper reports a compiler prototype for SIGNAL. Compared with the existing SIGNAL com- piler, we propose a new intermediate representation （named S-CGA, a variant of clocked guarded actions）, to integrate more synchronous programs into our compiler prototype in the future. The front-end of the compiler, i.e., the transla- tion from SIGNAL to S-CGA, is presented. As well, the proof of semantics preservation is mechanized in the theo- rem prover Coq. Moreover, we present the back-end of the compiler, including sequential code generation and multi- threaded code generation with time-predictable properties. With the rising importance of multi-core processors in safety- critical embedded systems or cyber-physical systems （CPS）, there is a growing need for model-driven generation of multi- threaded code and thus mapping on multi-core. We propose a time-predictable multi-core architecture model in archi- tecture analysis and design language （AADL）, and map the multi-threaded code to this model.展开更多
This paper presents a simple and safe compiler, called MinSIGNAL, from a subset of the synchronous dataflow language SIGNAL to C, as well as its existing en? hancements. The compiler follows a modular architecture, an...This paper presents a simple and safe compiler, called MinSIGNAL, from a subset of the synchronous dataflow language SIGNAL to C, as well as its existing en? hancements. The compiler follows a modular architecture, and can be seen as a sequence of source-to-source transformations applied to an intermediate representation which is named Synchronous Clocked Guarded Actions (S-CGA) and translation to sequential imperative code. Objective Caml (OCaml) is used for the implementation of MinSIGNAL. As a modem functional language, OCaml is adapted to symbolic computation and so, particularly suitable for compiler design and implementation of formal analysis tools. In particular, the safety of its type checking allows to skip some verification that would be mandatory with other languages. Additionally, this work is a basis for the formal verification of the compilation of SIGNAL with a theorem prover such as Coq.展开更多
能够提供更强计算能力的多核处理器将在安全关键系统中得到广泛应用,但是由于现代处理器所使用的流水线、乱序执行、动态分支预测、Cache等性能提高机制以及多核之间的资源共享,使得系统的最坏执行时间分析变得非常困难.为此,国际学术...能够提供更强计算能力的多核处理器将在安全关键系统中得到广泛应用,但是由于现代处理器所使用的流水线、乱序执行、动态分支预测、Cache等性能提高机制以及多核之间的资源共享,使得系统的最坏执行时间分析变得非常困难.为此,国际学术界提出时间可预测系统设计的思想,以降低系统的最坏执行时间分析难度.已有研究主要关注硬件层次及其编译方法的调整和优化,而较少关注软件层次,即,时间可预测多线程代码的构造方法以及到多核硬件平台的映射.提出一种基于同步语言模型驱动的时间可预测多线程代码生成方法,并对代码生成器的语义保持进行证明;提出一种基于AADL(architecture analysis and design language)的时间可预测多核体系结构模型,作为研究的目标平台;最后,给出多线程代码到多核体系结构模型的映射方法,并给出系统性质的分析框架.展开更多
基金Supported by the National Natural Science Foundation of China(No. 60375037 and 60543003).
文摘Objective:To examine and compare the synchronization of different brain regions during the Chinese and English Stroop tasks.Methods.Ten native Chinese speakers with a moderate command of English participated in this study,and event-related potentials were recorded while participants performed the Stroop task.Then wavelet-based estimation of instantaneous EEG coherence was applied to investigate the synchronization of different brain regions during Stroop task.Results:A greater negativity for the in- congruent situation than congruent situation appeared from 350ms to 600ms post-stimulus onset over frontal,central,and parietal regions in Chinese Stroop task,while the negativity was absent in English Stroop task.However,not only in Chinese Stroop task but also in English Stroop task was it found signif- icantly higher EEG coherences for the incongruent situation than congruent situation over frontal,pari- etal,and frontoparietal regions before 400ms post stimulus onset atβ(13-30 Hz) frequency band.Conclu- sion:This finding indicated that wavelet-based coherence is more exquisite tool to analyze brain electro- physiological signals associated with complex cognitive task than ERP component,and that functional syn- chronization indexed by EEG coherence is enhanced at the earlier stage while processing the conflicting in- formation for the incongruent stimulus.
文摘SIGNAL belongs to the synchronous languages family which are widely used in the design of safety-critical real-time systems such as avionics, space systems, and nu- clear power plants. This paper reports a compiler prototype for SIGNAL. Compared with the existing SIGNAL com- piler, we propose a new intermediate representation （named S-CGA, a variant of clocked guarded actions）, to integrate more synchronous programs into our compiler prototype in the future. The front-end of the compiler, i.e., the transla- tion from SIGNAL to S-CGA, is presented. As well, the proof of semantics preservation is mechanized in the theo- rem prover Coq. Moreover, we present the back-end of the compiler, including sequential code generation and multi- threaded code generation with time-predictable properties. With the rising importance of multi-core processors in safety- critical embedded systems or cyber-physical systems （CPS）, there is a growing need for model-driven generation of multi- threaded code and thus mapping on multi-core. We propose a time-predictable multi-core architecture model in archi- tecture analysis and design language （AADL）, and map the multi-threaded code to this model.
基金the National Natural Science Foundation of China (Grant No. 61502231)the Natural Science Foundation of Jiangsu Province (BK20150753)+4 种基金the National Defense Basic Scientific Research Project (JCKY2016203B011)the Project of the State Key Laboratory of Software Development Environment of China (SKLSDE- 2015KF-04)the Avionics Science Foundation of China (2015ZC52027)China Postdoctoral Science Foundation, and the Open Project of Shanghai Key Laboratory of Trustworthy Computing (07dz22304201502)the RTRA STAE Foundation in France.
文摘This paper presents a simple and safe compiler, called MinSIGNAL, from a subset of the synchronous dataflow language SIGNAL to C, as well as its existing en? hancements. The compiler follows a modular architecture, and can be seen as a sequence of source-to-source transformations applied to an intermediate representation which is named Synchronous Clocked Guarded Actions (S-CGA) and translation to sequential imperative code. Objective Caml (OCaml) is used for the implementation of MinSIGNAL. As a modem functional language, OCaml is adapted to symbolic computation and so, particularly suitable for compiler design and implementation of formal analysis tools. In particular, the safety of its type checking allows to skip some verification that would be mandatory with other languages. Additionally, this work is a basis for the formal verification of the compilation of SIGNAL with a theorem prover such as Coq.
文摘能够提供更强计算能力的多核处理器将在安全关键系统中得到广泛应用,但是由于现代处理器所使用的流水线、乱序执行、动态分支预测、Cache等性能提高机制以及多核之间的资源共享,使得系统的最坏执行时间分析变得非常困难.为此,国际学术界提出时间可预测系统设计的思想,以降低系统的最坏执行时间分析难度.已有研究主要关注硬件层次及其编译方法的调整和优化,而较少关注软件层次,即,时间可预测多线程代码的构造方法以及到多核硬件平台的映射.提出一种基于同步语言模型驱动的时间可预测多线程代码生成方法,并对代码生成器的语义保持进行证明;提出一种基于AADL(architecture analysis and design language)的时间可预测多核体系结构模型,作为研究的目标平台;最后,给出多线程代码到多核体系结构模型的映射方法,并给出系统性质的分析框架.
