Accurate time synchronization is fundamental to the correct and efficient operation of Wireless Sensor Networks(WSNs),especially in security-critical,time-sensitive applications.However,most existing protocols degrade...Accurate time synchronization is fundamental to the correct and efficient operation of Wireless Sensor Networks(WSNs),especially in security-critical,time-sensitive applications.However,most existing protocols degrade substantially under malicious interference.We introduce iSTSP,an Intelligent and Secure Time Synchronization Protocol that implements a four-stage defense pipeline to ensure robust,precise synchronization even in hostile environments:(1)trust preprocessing that filters node participation using behavioral trust scoring;(2)anomaly isolation employing a lightweight autoencoder to detect and excise malicious nodes in real time;(3)reliability-weighted consensus that prioritizes high-trust nodes during time aggregation;and(4)convergence-optimized synchronization that dynamically adjusts parameters using theoretical stability bounds.We provide rigorous convergence analysis including a closed-form expression for convergence time,and validate the protocol through both simulations and realworld experiments on a controlled 16-node testbed.Under Sybil attacks with five malicious nodes within this testbed,iSTSP maintains synchronization error increases under 12%and achieves a rapid convergence.Compared to state-ofthe-art protocols like TPSN,SE-FTSP,and MMAR-CTS,iSTSP offers 60%faster detection,broader threat coverage,and more than 7 times lower synchronization error,with a modest 9.3%energy overhead over 8 h.We argue this is an acceptable trade-off for mission-critical deployments requiring guaranteed security.These findings demonstrate iSTSP’s potential as a reliable solution for secure WSN synchronization and motivate future work on large-scale IoT deployments and integration with energy-efficient communication protocols.展开更多
Rollback is a synchronization mechanism in optimistic parallel discrete event simulation （PDES）. A basic and popular realization of rollback is based on cancellation of error executed messages. In this paper, severa...Rollback is a synchronization mechanism in optimistic parallel discrete event simulation （PDES）. A basic and popular realization of rollback is based on cancellation of error executed messages. In this paper, several cancellation strategies are introduced, and a new method proposed. Performance comparison is made based on experimental results.展开更多
The IEEE 1588 precision time protocol(PTP)is very important for many industrial sectors and applications that require time synchronization accuracy between computers down to microsecond and even nanosecond levels.Neve...The IEEE 1588 precision time protocol(PTP)is very important for many industrial sectors and applications that require time synchronization accuracy between computers down to microsecond and even nanosecond levels.Nevertheless,PTP and its underlying network infrastructure are vulnerable to cyber-attacks,which can stealthily reduce the time synchronization accuracy to unacceptable and even damage-causing levels for individual clocks or an entire network,leading to financial loss or even physical destruction.Existing security protocol extensions only partially address this problem.This paper provides a comprehensive analysis of strategies for advanced persistent threats to PTP infrastructure,possible attacker locations,and the impact on clock and network synchronization in the presence of security protocol extensions,infrastructure redundancy,and protocol redundancy.It distinguishes between attack strategies and attacker types as described in RFC7384,but further distinguishes between the spoofing and time source attack,the simple internal attack,and the advanced internal attack.Some experiments were conducted to demonstrate the impact of PTP attacks.Our analysis shows that a sophisticated attacker has a range of methodologies to compromise a PTP network.Moreover,all PTP infrastructure components can host an attacker,making the comprehensive protection of a PTP network against a malware infiltration,as for example exercised by Stuxnet,a very tedious task.展开更多
High performance computer （HPC） is a complex huge system, of which the architecture design meets increasing difficulties and risks. Traditional methods, such as theoretical analysis, component-level simulation and s...High performance computer （HPC） is a complex huge system, of which the architecture design meets increasing difficulties and risks. Traditional methods, such as theoretical analysis, component-level simulation and sequential simulation, are not applicable to system-level simulations of HPC systems. Even the parallel simulation using large-scale parallel machines also have many difficulties in scalability, reliability, generality, as well as efficiency. According to the current needs of HPC architecture design, this paper proposes a system-level parallel simulation platform： ArchSim. We first introduce the architecture of ArchSim simulation platform which is composed of a global server （GS）, local server agents （LSA） and entities. Secondly, we emphasize some key techniques of ArchSim, including the synchronization protocol, the communication mechanism and the distributed checkpointing/restart mechanism. We then make a synthesized test of some main performance indices of ArchSim with the phold benchmark and analyze the extra overhead generated by ArchSim. Finally, based on ArchSim, we construct a parallel event-driven interconnection network simulator and a system-level simulator for a small scale HPC system with 256 processors. The results of the performance test and HPC system simulations demonstrate that ArchSim can achieve high speedup ratio and high scalability on parallel host machine and support system-level simulations for the architecture design of HPC systems.展开更多
基金this project under Geran Putra Inisiatif(GPI)with reference of GP-GPI/2023/976210。
文摘Accurate time synchronization is fundamental to the correct and efficient operation of Wireless Sensor Networks(WSNs),especially in security-critical,time-sensitive applications.However,most existing protocols degrade substantially under malicious interference.We introduce iSTSP,an Intelligent and Secure Time Synchronization Protocol that implements a four-stage defense pipeline to ensure robust,precise synchronization even in hostile environments:(1)trust preprocessing that filters node participation using behavioral trust scoring;(2)anomaly isolation employing a lightweight autoencoder to detect and excise malicious nodes in real time;(3)reliability-weighted consensus that prioritizes high-trust nodes during time aggregation;and(4)convergence-optimized synchronization that dynamically adjusts parameters using theoretical stability bounds.We provide rigorous convergence analysis including a closed-form expression for convergence time,and validate the protocol through both simulations and realworld experiments on a controlled 16-node testbed.Under Sybil attacks with five malicious nodes within this testbed,iSTSP maintains synchronization error increases under 12%and achieves a rapid convergence.Compared to state-ofthe-art protocols like TPSN,SE-FTSP,and MMAR-CTS,iSTSP offers 60%faster detection,broader threat coverage,and more than 7 times lower synchronization error,with a modest 9.3%energy overhead over 8 h.We argue this is an acceptable trade-off for mission-critical deployments requiring guaranteed security.These findings demonstrate iSTSP’s potential as a reliable solution for secure WSN synchronization and motivate future work on large-scale IoT deployments and integration with energy-efficient communication protocols.
基金Project supported by Applied Materials Foundation of ShanghaiMunicipal Commission of Science and Technology ( Grant No .0215)
文摘Rollback is a synchronization mechanism in optimistic parallel discrete event simulation （PDES）. A basic and popular realization of rollback is based on cancellation of error executed messages. In this paper, several cancellation strategies are introduced, and a new method proposed. Performance comparison is made based on experimental results.
基金the Technical and Vocational Training Corporation, Saudi Arabia.
文摘The IEEE 1588 precision time protocol(PTP)is very important for many industrial sectors and applications that require time synchronization accuracy between computers down to microsecond and even nanosecond levels.Nevertheless,PTP and its underlying network infrastructure are vulnerable to cyber-attacks,which can stealthily reduce the time synchronization accuracy to unacceptable and even damage-causing levels for individual clocks or an entire network,leading to financial loss or even physical destruction.Existing security protocol extensions only partially address this problem.This paper provides a comprehensive analysis of strategies for advanced persistent threats to PTP infrastructure,possible attacker locations,and the impact on clock and network synchronization in the presence of security protocol extensions,infrastructure redundancy,and protocol redundancy.It distinguishes between attack strategies and attacker types as described in RFC7384,but further distinguishes between the spoofing and time source attack,the simple internal attack,and the advanced internal attack.Some experiments were conducted to demonstrate the impact of PTP attacks.Our analysis shows that a sophisticated attacker has a range of methodologies to compromise a PTP network.Moreover,all PTP infrastructure components can host an attacker,making the comprehensive protection of a PTP network against a malware infiltration,as for example exercised by Stuxnet,a very tedious task.
基金supported by the National High Technology Research and Development 863 Program of China under Grant No. 2007AA01Z117the National Basic Research 973 Program of China under Grant No.2007CB310900
文摘High performance computer （HPC） is a complex huge system, of which the architecture design meets increasing difficulties and risks. Traditional methods, such as theoretical analysis, component-level simulation and sequential simulation, are not applicable to system-level simulations of HPC systems. Even the parallel simulation using large-scale parallel machines also have many difficulties in scalability, reliability, generality, as well as efficiency. According to the current needs of HPC architecture design, this paper proposes a system-level parallel simulation platform： ArchSim. We first introduce the architecture of ArchSim simulation platform which is composed of a global server （GS）, local server agents （LSA） and entities. Secondly, we emphasize some key techniques of ArchSim, including the synchronization protocol, the communication mechanism and the distributed checkpointing/restart mechanism. We then make a synthesized test of some main performance indices of ArchSim with the phold benchmark and analyze the extra overhead generated by ArchSim. Finally, based on ArchSim, we construct a parallel event-driven interconnection network simulator and a system-level simulator for a small scale HPC system with 256 processors. The results of the performance test and HPC system simulations demonstrate that ArchSim can achieve high speedup ratio and high scalability on parallel host machine and support system-level simulations for the architecture design of HPC systems.
