为解决SONiC(software for open networking in the cloud)交换机操作系统对多模态网络(polymor phic network,PINet)中模态适配及模态管控问题,提出了一个基于P4Runtime的SONiC网元控制通道容器p4runtime-pins,使多模态网元设备可以支...为解决SONiC(software for open networking in the cloud)交换机操作系统对多模态网络(polymor phic network,PINet)中模态适配及模态管控问题,提出了一个基于P4Runtime的SONiC网元控制通道容器p4runtime-pins,使多模态网元设备可以支持多种网络模态流表的配置。p4runtime-pins容器通过gRPC服务模块实现与控制器的连接,使用邻近网元发现算法实现控制器对链路的发现。设计了网元端口更新算法解决了网元设备在实际应用环境中存在的端口变更问题。同时,针对SONiC网元交换机中硬件转发处理单元存在的流表支持性差异问题,设计了内部流表转存和gRPC网元代理功能,实现了不同网络模态流表的部署。实验结果表明,p4runtime-pins容器资源消耗低,仅占用了1.70%的CPU资源和0.45%的内存资源。同时,部署p4runtime-pins容器的SONiC网元设备能够准确地接收并配置控制器下发的流表规则,流表配置延迟仅为0.027~0.037 s。展开更多
A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional ...A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O, and 16kbit dual port block RAM. Its die size is 6. 104mm× 6. 620mm, with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.展开更多
文摘为解决SONiC(software for open networking in the cloud)交换机操作系统对多模态网络(polymor phic network,PINet)中模态适配及模态管控问题,提出了一个基于P4Runtime的SONiC网元控制通道容器p4runtime-pins,使多模态网元设备可以支持多种网络模态流表的配置。p4runtime-pins容器通过gRPC服务模块实现与控制器的连接,使用邻近网元发现算法实现控制器对链路的发现。设计了网元端口更新算法解决了网元设备在实际应用环境中存在的端口变更问题。同时,针对SONiC网元交换机中硬件转发处理单元存在的流表支持性差异问题,设计了内部流表转存和gRPC网元代理功能,实现了不同网络模态流表的部署。实验结果表明,p4runtime-pins容器资源消耗低,仅占用了1.70%的CPU资源和0.45%的内存资源。同时,部署p4runtime-pins容器的SONiC网元设备能够准确地接收并配置控制器下发的流表规则,流表配置延迟仅为0.027~0.037 s。
文摘A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O, and 16kbit dual port block RAM. Its die size is 6. 104mm× 6. 620mm, with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.
