A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge...A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.展开更多
This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-...This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-type conductive pillars,three p-type conductive pillars,an oxide trench under the gate,and a light n-type current spreading layer(NCSL)under the p-body.The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer,thus improving the specific on-resistance(R_(on,sp)).There are three p-type pillars in the modified structure,with the p-type pillars on both sides playing the same role.The p-type conductive pillars relieve the electric field(E-field)in the corner of the trench bottom.Two-dimensional simulation(silvaco TCAD)indicates that Ron,sp of the modified structure,and breakdown voltage(V_(BR))are improved by 22.2%and 21.1%respectively,while the maximum figure of merit(FOM=V_(BR)^(2)/R_(on,sp)) is improved by 79.0%.Furthermore,the improved structure achieves a light smaller low gate-to-drain charge(Q_(gd))and when compared with the conventional UMOSFET(conventional-UMOS),it displays great advantages for reducing the switching energy loss.These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance,which also enables the charge carriers to be extracted quickly.In the end,under the condition of the same total charge quantity,the simulation comparison of gate charge and OFF-state characteristics between Gaussdoped structure and uniform-doped structure shows that Gauss-doped structure increases the V_(BR)of the device without degradation of dynamic performance.展开更多
A deep trench super-junction LDMOS with double charge compensation layer(DC DT SJ LDMOS)is proposed in this paper.Due to the capacitance effect of the deep trench which is known as silicon-insulator-silicon(SIS)capaci...A deep trench super-junction LDMOS with double charge compensation layer(DC DT SJ LDMOS)is proposed in this paper.Due to the capacitance effect of the deep trench which is known as silicon-insulator-silicon(SIS)capacitance,the charge balance in the super-junction region of the conventional deep trench SJ LDMOS(Con.DT SJ LDMOS)device will be broken,resulting in breakdown voltage(BV)of the device drops.DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con.DT SJ LDMOS device.Therefore,the drift region reaches an ideal charge balance state again.The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply,meanwhile the enlarged on-current region reduces its specific on-resistance.The simulation results show that compared with the Con.DT SJ LD-MOS,the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V,and the R_(on,sp) decreased to 23.7 mΩ·cm^(2).展开更多
A new super-junction lateral double diffused MOSFET （LDMOST） structure is designed with n-type charge compensation layer embedded in the p^--substrate near the drain to suppress substrate-assisted depletion effect t...A new super-junction lateral double diffused MOSFET （LDMOST） structure is designed with n-type charge compensation layer embedded in the p^--substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p^--substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field （REBULF） is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain, The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.展开更多
A novel 1200 V SiC super-junction(SJ)MOSFET with a partially widened pillar structure is proposed and investi-gated by using the two-dimensional numerical simulation tool.Based on the SiC SJ MOSFET structure,a partial...A novel 1200 V SiC super-junction(SJ)MOSFET with a partially widened pillar structure is proposed and investi-gated by using the two-dimensional numerical simulation tool.Based on the SiC SJ MOSFET structure,a partially widened P-region is added at the SJ pillar region to improve the short-circuit(SC)ability.After investigating the position and doping concentration of the widened P-region,an optimal structure is determined.From the simulation results,the SC withstand times(SCWTs)of the conventional trench MOSFET(CT-MOSFET),the SJ MOSFET,and the proposed structure at 800 V DC bus voltage are 15μs,17μs,and 24μs,respectively.The SCWTs of the proposed structure are increased by 60%and 41.2%in comparison with that of the other two structures.The main reason for the proposed structure with an enhanced SC capability is related to the effective suppression of saturation current at the high DC bias conditions by using a modu-lated P-pillar region.Meanwhile,a good Baliga's FOM(BV^(2)/R_(on))also can be achieved in the proposed structure due to the advantage of the SJ structure.In addition,the fabrication technology of the proposed structure is compatible with the standard epitaxy growth method used in the SJ MOSFET.As a result,the SJ structure with this feasible optimization skill presents an effect on improving the SC reliability of the SiC SJ MOSFET without the degeneration of the Baliga's FOM.展开更多
In this paper, we propose a novel low on-resistance Super Junction （S J） Lateral Double-diffusion MOSFET （LDMOST） which has split p column structures with rated voltage of 60-100V. The key feature of this new stru...In this paper, we propose a novel low on-resistance Super Junction （S J） Lateral Double-diffusion MOSFET （LDMOST） which has split p column structures with rated voltage of 60-100V. The key feature of this new structure is that the split p column super junction primarily provides the low on-resistance path and it just locates at the surface of the drift region rather than the entire drift region. The manufacturing process of the device is relatively simple and is compatible with the Bi-CMOS process. Three dimension device simulations indicate that this structure can achieve a low specific on-resistance of 11.5 mΩ·cm^2 at a gate voltage of 5 V compared with 27.7 mΩ·cm^2 for the conventional LDMOST at the breakdown voltage of 80V.展开更多
A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the...A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.展开更多
An improved trench gate super-junction insulated-gate bipolar transistor is presented. The improved structure contains two emitter regions. The first emitter region of the device works as the conventional structure,wh...An improved trench gate super-junction insulated-gate bipolar transistor is presented. The improved structure contains two emitter regions. The first emitter region of the device works as the conventional structure,which can absorb both the electron current and hole current. The second emitter on the top of the p-pillar acts as the hole current diverter, leading to an improved latch-up capability without sacrificing the off-state breakdown voltage（BV） and turn-off loss. The simulation shows that the latch-up limit of the SJ-IGBT increases from 15000 to 28300 A/cm^2 at VGE D10 V, the BV is 810 V, and the turn off loss is 6.5 m J/cm^2 at Von D1.2 V.展开更多
As a type of charge-balanced power device,the performance of super-junction MOSFETs(SJ-MOS)is significantly influ-enced by fluctuations in the fabrication process.To overcome the relatively narrow process window of co...As a type of charge-balanced power device,the performance of super-junction MOSFETs(SJ-MOS)is significantly influ-enced by fluctuations in the fabrication process.To overcome the relatively narrow process window of conventional SJ-MOS,an optimized structure"vertical variable doping super-junction MOSFET(VVD-SJ)"is proposed.Based on the analysis using the charge superposition principle,it is observed that the VVD-SJ,in which the impurity concentration of the P-pillar gradually decreases while that of the N-pillar increases from top to bottom,improves the electric field distribution and mitigates charge imbalance(CIB).Experimental results demonstrate that the optimized 600 V VVD-SJ achieves a 35.90%expansion of the pro-cess window.展开更多
An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utili...An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD simulations.The optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the p-pillar.The improved structure is named as SNPPT-MOS.The side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state mode.The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.展开更多
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201)the National Natural Science Foundation of China (Grant No. 61176069)the National Defense Pre-Research of China (Grant No. 51308020304)
文摘A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.
基金the National Natural Science Foundation of China(Grant Nos.61774052 and 61904045)the Youth Foundation of the Education Department of Jiangxi Province,China(Grant No.GJJ191154)the Youth Foundation of Ping Xiang University,China(Grant No.2018D0230).
文摘This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-type conductive pillars,three p-type conductive pillars,an oxide trench under the gate,and a light n-type current spreading layer(NCSL)under the p-body.The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer,thus improving the specific on-resistance(R_(on,sp)).There are three p-type pillars in the modified structure,with the p-type pillars on both sides playing the same role.The p-type conductive pillars relieve the electric field(E-field)in the corner of the trench bottom.Two-dimensional simulation(silvaco TCAD)indicates that Ron,sp of the modified structure,and breakdown voltage(V_(BR))are improved by 22.2%and 21.1%respectively,while the maximum figure of merit(FOM=V_(BR)^(2)/R_(on,sp)) is improved by 79.0%.Furthermore,the improved structure achieves a light smaller low gate-to-drain charge(Q_(gd))and when compared with the conventional UMOSFET(conventional-UMOS),it displays great advantages for reducing the switching energy loss.These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance,which also enables the charge carriers to be extracted quickly.In the end,under the condition of the same total charge quantity,the simulation comparison of gate charge and OFF-state characteristics between Gaussdoped structure and uniform-doped structure shows that Gauss-doped structure increases the V_(BR)of the device without degradation of dynamic performance.
文摘A deep trench super-junction LDMOS with double charge compensation layer(DC DT SJ LDMOS)is proposed in this paper.Due to the capacitance effect of the deep trench which is known as silicon-insulator-silicon(SIS)capacitance,the charge balance in the super-junction region of the conventional deep trench SJ LDMOS(Con.DT SJ LDMOS)device will be broken,resulting in breakdown voltage(BV)of the device drops.DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con.DT SJ LDMOS device.Therefore,the drift region reaches an ideal charge balance state again.The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply,meanwhile the enlarged on-current region reduces its specific on-resistance.The simulation results show that compared with the Con.DT SJ LD-MOS,the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V,and the R_(on,sp) decreased to 23.7 mΩ·cm^(2).
基金Project supported by the National Natural Science Foundation of China （Grant No 60436030） and the Key Laboratory for Defence Science and Technology on Military Simulation Integrated Circuits （Grant No 9140C0903010604）.
文摘A new super-junction lateral double diffused MOSFET （LDMOST） structure is designed with n-type charge compensation layer embedded in the p^--substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p^--substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field （REBULF） is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain, The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.
基金Project supported by the Key Research and Development Program of Guangdong Province,China(Grant No.2019B090917010).
文摘A novel 1200 V SiC super-junction(SJ)MOSFET with a partially widened pillar structure is proposed and investi-gated by using the two-dimensional numerical simulation tool.Based on the SiC SJ MOSFET structure,a partially widened P-region is added at the SJ pillar region to improve the short-circuit(SC)ability.After investigating the position and doping concentration of the widened P-region,an optimal structure is determined.From the simulation results,the SC withstand times(SCWTs)of the conventional trench MOSFET(CT-MOSFET),the SJ MOSFET,and the proposed structure at 800 V DC bus voltage are 15μs,17μs,and 24μs,respectively.The SCWTs of the proposed structure are increased by 60%and 41.2%in comparison with that of the other two structures.The main reason for the proposed structure with an enhanced SC capability is related to the effective suppression of saturation current at the high DC bias conditions by using a modu-lated P-pillar region.Meanwhile,a good Baliga's FOM(BV^(2)/R_(on))also can be achieved in the proposed structure due to the advantage of the SJ structure.In addition,the fabrication technology of the proposed structure is compatible with the standard epitaxy growth method used in the SJ MOSFET.As a result,the SJ structure with this feasible optimization skill presents an effect on improving the SC reliability of the SiC SJ MOSFET without the degeneration of the Baliga's FOM.
基金Supported by National Natural Science Foundation of China. (No. 60576052) and The Key Program Project of National Science Foundation of China. (No. 60436030)
文摘In this paper, we propose a novel low on-resistance Super Junction （S J） Lateral Double-diffusion MOSFET （LDMOST） which has split p column structures with rated voltage of 60-100V. The key feature of this new structure is that the split p column super junction primarily provides the low on-resistance path and it just locates at the surface of the drift region rather than the entire drift region. The manufacturing process of the device is relatively simple and is compatible with the Bi-CMOS process. Three dimension device simulations indicate that this structure can achieve a low specific on-resistance of 11.5 mΩ·cm^2 at a gate voltage of 5 V compared with 27.7 mΩ·cm^2 for the conventional LDMOST at the breakdown voltage of 80V.
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2010ZX02201)the National Natural Science Foundation of China(No.61176069)the National Defense Pre-Research of China(No.51308020304)
文摘A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.
基金Project supported by the National Natural Science Foundation of China(No.61204083)the Natural Science Foundation of the Jiangsu Province of China(Nos.BK2012204,BY2011146)the Scientific Research Guidance Foundation of Southeast University Wuxi Branch Campus
文摘An improved trench gate super-junction insulated-gate bipolar transistor is presented. The improved structure contains two emitter regions. The first emitter region of the device works as the conventional structure,which can absorb both the electron current and hole current. The second emitter on the top of the p-pillar acts as the hole current diverter, leading to an improved latch-up capability without sacrificing the off-state breakdown voltage（BV） and turn-off loss. The simulation shows that the latch-up limit of the SJ-IGBT increases from 15000 to 28300 A/cm^2 at VGE D10 V, the BV is 810 V, and the turn off loss is 6.5 m J/cm^2 at Von D1.2 V.
基金supported by the National Science Foundation of Guangdong Province under Grant 2023A1515012652School-enterprise cooperation projects of ZTE Corporation.
文摘As a type of charge-balanced power device,the performance of super-junction MOSFETs(SJ-MOS)is significantly influ-enced by fluctuations in the fabrication process.To overcome the relatively narrow process window of conventional SJ-MOS,an optimized structure"vertical variable doping super-junction MOSFET(VVD-SJ)"is proposed.Based on the analysis using the charge superposition principle,it is observed that the VVD-SJ,in which the impurity concentration of the P-pillar gradually decreases while that of the N-pillar increases from top to bottom,improves the electric field distribution and mitigates charge imbalance(CIB).Experimental results demonstrate that the optimized 600 V VVD-SJ achieves a 35.90%expansion of the pro-cess window.
基金the National Natural Science Foundation of China(Grant Nos.61774052 and 61904045)the National Natural Science Foundation of Jiangxi Province of China(Grant No.20202BABL201021)the Education Department of Jiangxi Province of China for Youth Foundation(Grant No.GJJ191154)。
文摘An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD simulations.The optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the p-pillar.The improved structure is named as SNPPT-MOS.The side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state mode.The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.
