In this paper,we analytically study the relationship between the coercive field,remnant polarization and the thickness of a ferroelectric material,required for the minimum subthreshold swing in a negative capacitance ...In this paper,we analytically study the relationship between the coercive field,remnant polarization and the thickness of a ferroelectric material,required for the minimum subthreshold swing in a negative capacitance capacitor.The interdependence of the ferroelectric material properties shown in this study is defined by the capacitance matching conditions in the subthreshold region in an NC capacitor.In this paper,we propose an analytical model to find the optimal ferroelectric thickness and channel doping to achieve a minimum subthreshold swing,due to a particular ferroelectric material.Our results have been validated against the numerical and experimental results already available in the literature.Furthermore,we obtain the minimum possible subthreshold swing for different ferroelectric materials used in the gate stack of an NC-FET in the context of a manufacturable semiconductor technology.Our results are presented in the form of a table,which shows the calculated channel doping,ferroelectric thickness and minimum subthreshold for five different ferroelectric materials.展开更多
Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models i...Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.展开更多
The present work gives some insight into the subthreshold behaviour of short-channel double-material- gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formu- latio...The present work gives some insight into the subthreshold behaviour of short-channel double-material- gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formu- lation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLASTM by Silvaco Inc.展开更多
In order to improve the drive current and subthreshold swing（SS）, a novel vertical-dual-source tunneling field-effect transistor（VDSTFET） device is proposed in this paper. The influence of source height, channel l...In order to improve the drive current and subthreshold swing（SS）, a novel vertical-dual-source tunneling field-effect transistor（VDSTFET） device is proposed in this paper. The influence of source height, channel length and channel thickness on the device are investigated through two-dimensional numerical simulations. Si-VDSTFET have greater tunneling area and thinner channel, showing an on-current as high as 1.24 A at gate voltage of 0.8 V and drain voltage of 0.5 V, off-current of less than 0.1 f A, an improved average subthreshold swing of 14 m V/dec,and a minimum point slope of 4 m V/dec.展开更多
In this work,a conventional HfO_(2) gate dielectric layer is replaced with a 3-nm ferroelectric(Fe) HZO layer in the gate stacks of advanced fin field-effect transistors(FinFETs).Fe-induced characteristics,e.g.,negati...In this work,a conventional HfO_(2) gate dielectric layer is replaced with a 3-nm ferroelectric(Fe) HZO layer in the gate stacks of advanced fin field-effect transistors(FinFETs).Fe-induced characteristics,e.g.,negative drain induced barrier lowering(N-DIBL) and negative differential resistance(NDR),are clearly observed for both p-and n-type HZO-based FinFETs.These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide(HZO) film,caused by Al doping from the TiAlC capping layer.This mechanism is verified for capacitors with structures similar to the FinFETs.Owing to the enhanced ferroelectricity and N-DIBL phenomenon,the drain current(I_(DS))of the HZO-FinFETs is greater than that of HfO_(2)-FinFETs and obtained at a lower operating voltage.Accordingly,circuits based on HZO-FinFET achieve higher performance than those based on HfO_(2)-FinFET at a low voltage drain(V_(DD)),which indicates the application feasibility of the HZO-FinFETs in the ultralow power integrated circuits.展开更多
In this letter,an enhancement-mode(E-mode)GaN p-channel field-effect transistor(p-FET)with a high current den-sity of−4.9 mA/mm based on a O_(3)-Al_(2)O_(3)/HfO_(2)(5/15 nm)stacked gate dielectric was demonstrated on ...In this letter,an enhancement-mode(E-mode)GaN p-channel field-effect transistor(p-FET)with a high current den-sity of−4.9 mA/mm based on a O_(3)-Al_(2)O_(3)/HfO_(2)(5/15 nm)stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure.Attributed to the p++-GaN capping layer,a good linear ohmic I−V characteristic fea-turing a low-contact resistivity(ρc)of 1.34×10^(−4)Ω·cm^(2) was obtained.High gate leakage associated with the HfO_(2)high-k gate dielectric was effectively blocked by the 5-nm O_(3)-Al_(2)O_(3)insertion layer grown by atomic layer deposition,contributing to a high ION/IOFF ratio of 6×10^(6)and a remarkably reduced subthreshold swing(SS)in the fabricated p-FETs.The proposed structure is compelling for energy-efficient GaN complementary logic(CL)circuits.展开更多
A Ⅲ-Ⅴ heterojunction tunneling field-effect transistor(TFET) can enhance the on-state current effectively,and GaAsSb/InGaAs heterojunction exhibits better performance with the adjustable band alignment by modulating...A Ⅲ-Ⅴ heterojunction tunneling field-effect transistor(TFET) can enhance the on-state current effectively,and GaAsSb/InGaAs heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition.In this paper,the performance of the cylindrical surrounding-gate GaAsSb/InGaAs heterojunction TFET with gate-drain underlap is investigated by numerical simulation.We validate that reducing drain doping concentration and increasing gate-drain underlap could be effective ways to reduce the off-state current and subthreshold swing(SS),while increasing source doping concentration and adjusting the composition of GaAsSbInGaAs can improve the on-state current.In addition,the resonant TFET based on GaAsSb/InGaAs is also studied,and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current,respectively,and is much superior to the conventional TFET.展开更多
The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used...The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.展开更多
Cold-source field-effect transistors(CS-FETs)have been developed to overcome the major challenge of power dissipation in modern integrated circuits.Cold metals suitable for n-type CS-FETs have been proposed as the ide...Cold-source field-effect transistors(CS-FETs)have been developed to overcome the major challenge of power dissipation in modern integrated circuits.Cold metals suitable for n-type CS-FETs have been proposed as the ideal electrode to filter the high-energy electrons and break the thermal limit on subthreshold swing(SS).In this work,regarding the p-type CS-FETs,we propose TcX_(2) and ReX_(2)(X=S,Se)as the injection source to realize the sub-thermal switching for holes.First-principles calculations unveils the cold-metal characteristics of monolayer TcX_(2) and ReX_(2),possessing a sub-gap below the Fermi level and a decreasing DOS with energy.Quantum device simulations demonstrate that TcX_(2) and ReX_(2) can enable the cold source effects in WSe_(2) p-type FETs,achieving steep SS of 29-38 mV/dec and high on/off ratios of(2.3-5.6)×10^(7).Moreover,multilayer Re S2retains the cold metal characteristic,thus ensuring similar CS-FET performances to that of the monolayer source.This work underlines the significance of cold metals for the design of p-type CS-FETs.展开更多
A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress(NBS)is observed for amorphous InGaZnO(a-IGZO)thin-film transistors(TFTs),which can r...A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress(NBS)is observed for amorphous InGaZnO(a-IGZO)thin-film transistors(TFTs),which can recover in a short time.After comparing with the degradation phenomena under negative bias illumination stress(NBIS),positive bias stress(PBS),and positive bias illumination stress(PBIS),degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies(V_(o)^(+))in addition to the commonly reported doubly charged oxygen vacancies(V_(o)^(2+)).Furthermore,the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of V_(o)^(+)under positive gate bias.The proposed degradation mechanisms are verified by TCAD simulation.展开更多
The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characte...The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.展开更多
Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low...Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here,we investigate the TFETs based on two different integration types： in-plane and vertical heterostructures composed of two kinds of layered phosphorous（β-P and δ-P） by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio（PVR）when the intrinsic region length is near zero. Compared with the in-plane TFET based on β-P and δ-P, better performance with a higher on/off current ratio of - 10-6 and a steeper subthreshold swing（SS） of - 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of theβ-P and δ-P layers in the in-plane and vertical heterostructures.展开更多
In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combina...In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combination annealing,and chemical solution etching.The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm.After finishing the fabrication of devices,we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch.A poly-Si/SiGe core-shell JAMFETs was successfully demonstrated and it also exhibits a superior subthreshold swing of 81mV/dec and high on/off ratio>10^5 when annealing for 1hr at 600℃.The thermal diffusion process condition for this study are 1hr at 600℃ and 6hr at 700℃ for comparison.The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other.Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film.Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e.at higher temperature.This new process can still fabricate a comparable performance to classical planar FinFET in driving current.展开更多
文摘In this paper,we analytically study the relationship between the coercive field,remnant polarization and the thickness of a ferroelectric material,required for the minimum subthreshold swing in a negative capacitance capacitor.The interdependence of the ferroelectric material properties shown in this study is defined by the capacitance matching conditions in the subthreshold region in an NC capacitor.In this paper,we propose an analytical model to find the optimal ferroelectric thickness and channel doping to achieve a minimum subthreshold swing,due to a particular ferroelectric material.Our results have been validated against the numerical and experimental results already available in the literature.Furthermore,we obtain the minimum possible subthreshold swing for different ferroelectric materials used in the gate stack of an NC-FET in the context of a manufacturable semiconductor technology.Our results are presented in the form of a table,which shows the calculated channel doping,ferroelectric thickness and minimum subthreshold for five different ferroelectric materials.
基金supported by the National Natural Science Foundation of China(Grant No.61274112)
文摘Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.
文摘The present work gives some insight into the subthreshold behaviour of short-channel double-material- gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formu- lation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLASTM by Silvaco Inc.
基金Project supported by the National Natural Science Foundation of China(Nos.61204092,61574109)
文摘In order to improve the drive current and subthreshold swing（SS）, a novel vertical-dual-source tunneling field-effect transistor（VDSTFET） device is proposed in this paper. The influence of source height, channel length and channel thickness on the device are investigated through two-dimensional numerical simulations. Si-VDSTFET have greater tunneling area and thinner channel, showing an on-current as high as 1.24 A at gate voltage of 0.8 V and drain voltage of 0.5 V, off-current of less than 0.1 f A, an improved average subthreshold swing of 14 m V/dec,and a minimum point slope of 4 m V/dec.
基金financially supported by the Science and Technology Program of Beijing Municipal Science and Technology Commission (No.Z201100006820084)the National Natural Science Foundation of China (Nos.92064003,91964202 and 61904194)the Youth Innovation Promotion Association,Chinese Academy of Sciences under grant (Nos.2023130 and Y9YQ01R004)。
文摘In this work,a conventional HfO_(2) gate dielectric layer is replaced with a 3-nm ferroelectric(Fe) HZO layer in the gate stacks of advanced fin field-effect transistors(FinFETs).Fe-induced characteristics,e.g.,negative drain induced barrier lowering(N-DIBL) and negative differential resistance(NDR),are clearly observed for both p-and n-type HZO-based FinFETs.These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide(HZO) film,caused by Al doping from the TiAlC capping layer.This mechanism is verified for capacitors with structures similar to the FinFETs.Owing to the enhanced ferroelectricity and N-DIBL phenomenon,the drain current(I_(DS))of the HZO-FinFETs is greater than that of HfO_(2)-FinFETs and obtained at a lower operating voltage.Accordingly,circuits based on HZO-FinFET achieve higher performance than those based on HfO_(2)-FinFET at a low voltage drain(V_(DD)),which indicates the application feasibility of the HZO-FinFETs in the ultralow power integrated circuits.
基金This work was supported in part by the National Key Research and Development Program of China under Grant 2022YFB3604400in part by the Youth Innovation Promotion Association of Chinese Academy Sciences(CAS)+4 种基金in part by CAS-Croucher Funding Scheme under Grant CAS22801in part by National Natural Science Foundation of China under Grant 62074161,Grant 62004213,and Grant U20A20208in part by the Beijing Municipal Science and Technology Commission project under Grant Z201100008420009 and Grant Z211100007921018in part by the University of CASin part by IMECAS-HKUST-Joint Laboratory of Microelectronics.
文摘In this letter,an enhancement-mode(E-mode)GaN p-channel field-effect transistor(p-FET)with a high current den-sity of−4.9 mA/mm based on a O_(3)-Al_(2)O_(3)/HfO_(2)(5/15 nm)stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure.Attributed to the p++-GaN capping layer,a good linear ohmic I−V characteristic fea-turing a low-contact resistivity(ρc)of 1.34×10^(−4)Ω·cm^(2) was obtained.High gate leakage associated with the HfO_(2)high-k gate dielectric was effectively blocked by the 5-nm O_(3)-Al_(2)O_(3)insertion layer grown by atomic layer deposition,contributing to a high ION/IOFF ratio of 6×10^(6)and a remarkably reduced subthreshold swing(SS)in the fabricated p-FETs.The proposed structure is compelling for energy-efficient GaN complementary logic(CL)circuits.
基金Supported by the National Natural Science Foundation of China(No.60576066,No.60644007)the Natural Science Foundation of Anhui Province(No.2006kj012a).
基金supported by the National Natural Science Foundation of China(Grant Nos.61176038 and 61474093)the Science and Technology Planning Project of Guangdong Province,China(Grant No.2015A010103002)the Technology Development Program of Shaanxi Province,China(Grant No.2016GY-075)
文摘A Ⅲ-Ⅴ heterojunction tunneling field-effect transistor(TFET) can enhance the on-state current effectively,and GaAsSb/InGaAs heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition.In this paper,the performance of the cylindrical surrounding-gate GaAsSb/InGaAs heterojunction TFET with gate-drain underlap is investigated by numerical simulation.We validate that reducing drain doping concentration and increasing gate-drain underlap could be effective ways to reduce the off-state current and subthreshold swing(SS),while increasing source doping concentration and adjusting the composition of GaAsSbInGaAs can improve the on-state current.In addition,the resonant TFET based on GaAsSb/InGaAs is also studied,and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current,respectively,and is much superior to the conventional TFET.
基金Project supported by the National Ministries and Commissions,China (Grant Nos. 51308040203 and 6139801)the Fundamental Research Funds for the Central Universities,China (Grant Nos. 72105499 and 72104089)the Natural Science Basic Research Plan in Shaanxi Province,China (Grant No. 2010JQ8008)
文摘The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.
基金supported by the National Natural Science Foundation of China (Grant Nos.62034006,92264201,and 62104134)the Natural Science Foundation of Shandong Province of China (Grant Nos.ZR2023QF076 and ZR2023QF054)。
文摘Cold-source field-effect transistors(CS-FETs)have been developed to overcome the major challenge of power dissipation in modern integrated circuits.Cold metals suitable for n-type CS-FETs have been proposed as the ideal electrode to filter the high-energy electrons and break the thermal limit on subthreshold swing(SS).In this work,regarding the p-type CS-FETs,we propose TcX_(2) and ReX_(2)(X=S,Se)as the injection source to realize the sub-thermal switching for holes.First-principles calculations unveils the cold-metal characteristics of monolayer TcX_(2) and ReX_(2),possessing a sub-gap below the Fermi level and a decreasing DOS with energy.Quantum device simulations demonstrate that TcX_(2) and ReX_(2) can enable the cold source effects in WSe_(2) p-type FETs,achieving steep SS of 29-38 mV/dec and high on/off ratios of(2.3-5.6)×10^(7).Moreover,multilayer Re S2retains the cold metal characteristic,thus ensuring similar CS-FET performances to that of the monolayer source.This work underlines the significance of cold metals for the design of p-type CS-FETs.
基金Project supported in part by the National Natural Science Foundation of China(Grant Nos.61971299 and 61974101)the Natural Science Foundation of Jiangsu Province,China(Grant No.SBK2020021406)+2 种基金the Fund from the State Key Laboratory of ASIC and System,Fudan University(Grant No.2019KF007)the Fund from the Suzhou Science and Technology Bureau(Grant No.SYG201933)the Fund from the Jiangsu Higher Education Institute of China(Grant No.19KJB510058).
文摘A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress(NBS)is observed for amorphous InGaZnO(a-IGZO)thin-film transistors(TFTs),which can recover in a short time.After comparing with the degradation phenomena under negative bias illumination stress(NBIS),positive bias stress(PBS),and positive bias illumination stress(PBIS),degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies(V_(o)^(+))in addition to the commonly reported doubly charged oxygen vacancies(V_(o)^(2+)).Furthermore,the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of V_(o)^(+)under positive gate bias.The proposed degradation mechanisms are verified by TCAD simulation.
文摘The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11604019,61574020,and 61376018)the Ministry of Science and Technology of China(Grant No.2016YFA0301300)+1 种基金the Fund of State Key Laboratory of Information Photonics and Optical Communications(Beijing University of Posts and Telecommunications),Chinathe Fundamental Research Funds for the Central Universities,China(Grant No.2016RCGD22)
文摘Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here,we investigate the TFETs based on two different integration types： in-plane and vertical heterostructures composed of two kinds of layered phosphorous（β-P and δ-P） by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio（PVR）when the intrinsic region length is near zero. Compared with the in-plane TFET based on β-P and δ-P, better performance with a higher on/off current ratio of - 10-6 and a steeper subthreshold swing（SS） of - 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of theβ-P and δ-P layers in the in-plane and vertical heterostructures.
文摘In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combination annealing,and chemical solution etching.The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm.After finishing the fabrication of devices,we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch.A poly-Si/SiGe core-shell JAMFETs was successfully demonstrated and it also exhibits a superior subthreshold swing of 81mV/dec and high on/off ratio>10^5 when annealing for 1hr at 600℃.The thermal diffusion process condition for this study are 1hr at 600℃ and 6hr at 700℃ for comparison.The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other.Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film.Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e.at higher temperature.This new process can still fabricate a comparable performance to classical planar FinFET in driving current.
