A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） applications.Almost all of the previous subthreshold works ignore the leakage current in both active and st...A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） applications.Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes.To minimize leakage,a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty.Combined with buffering circuit and reconfigurable operation,the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region.Compared to the referenced subthreshold SRAM bitcell,the proposed bitcell shows：（1） a better critical state noise margin,and（2） smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13μW power consumption at 138 kHz frequency.展开更多
In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employe...In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.展开更多
This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM t...This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM to operate in the subthreshold region. The reverse short channel effect and the reverse narrow channel effect are utilized to improve the performance of the SRAM. A novel subthreshold pulse generation circuit produces an ideal pulse to make read operation stable. A floating write bit-line effectively reduces the standby leakage consumption. Finally, a short read bit-line makes the read operation fast and energy-saving. Measurements indicate that these techniques are effective, the SRAM can operate at 800 kHz and consume 1.94/zW at its lowest voltage （320 mV）.展开更多
We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （perfor...We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.展开更多
基金supported by the China State-Funded Study Abroad Program for High-Level Universities
文摘A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） applications.Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes.To minimize leakage,a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty.Combined with buffering circuit and reconfigurable operation,the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region.Compared to the referenced subthreshold SRAM bitcell,the proposed bitcell shows：（1） a better critical state noise margin,and（2） smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13μW power consumption at 138 kHz frequency.
文摘In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.
基金Project supported by the National Natural Science Foundation of China(No.61306039)the Next Generation of Information Technology for Sensing China(No.XDA06020401)
文摘This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM to operate in the subthreshold region. The reverse short channel effect and the reverse narrow channel effect are utilized to improve the performance of the SRAM. A novel subthreshold pulse generation circuit produces an ideal pulse to make read operation stable. A floating write bit-line effectively reduces the standby leakage consumption. Finally, a short read bit-line makes the read operation fast and energy-saving. Measurements indicate that these techniques are effective, the SRAM can operate at 800 kHz and consume 1.94/zW at its lowest voltage （320 mV）.
文摘We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.
